Rigid-Flexible Substrate for 3DIC Interconnection Warpage

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Solution Overview

Problem

The semiconductor industry faces challenges in miniaturization and packaging of semiconductor devices due to limitations in interconnection density and area constraints, particularly with stacked semiconductor devices like 3DICs, where uneven wafer warpage and high-pin-density connectors pose issues.

Innovation Solution

The use of rigid/flexible substrates with high-speed connectors and sockets allows for high-bandwidth interconnections between integrated circuit packages, overcoming area constraints and accommodating wafer warpage by providing flexible interconnections and enabling high-pin-density connectors for applications like data centers and AI servers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If stacked semiconductor devices (3DICs) are used to reduce physical size, then integration density is improved, but uneven wafer warpage and interconnection reliability deteriorate

Engineering Contradiction:
Improveintegration densityVSAvoidinterconnection reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent introduces an interposer substrate as an intermediary component between stacked semiconductor dies. This interposer provides a stable platform with controlled impedance traces and redistribution layers that mediate the interconnections between dies, isolating them from warpage effects and improving overall interconnection reliability while maintaining high integration density.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs underfill material with specific rheological parameters and curing characteristics to compensate for wafer warpage. By controlling the viscosity, flow characteristics, and thermal expansion parameters of the underfill, the system accommodates dimensional changes during processing and operation, maintaining reliable interconnections in stacked devices.

Inventive Principle:
Principle #35Parameter changes

2Power

If high-pin-density connectors are used to increase interconnection bandwidth, then data transmission capacity is improved, but manufacturing complexity and area constraints worsen

Engineering Contradiction:
Improveinterconnection bandwidthVSAvoidmanufacturing complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent transitions from planar interconnection layouts to three-dimensional stacked architectures with vertical interconnections through TSVs (through-silicon vias) and bump bonds. This dimensional change allows high-pin-density connectors to achieve greater bandwidth by utilizing the vertical dimension, effectively multiplying the interconnection capacity without increasing the footprint area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The interposer substrate serves multiple functions simultaneously: it provides mechanical support, enables impedance control for high-speed signals, facilitates bump bond formation, and allows redistribution of interconnection patterns. This multi-functionality consolidates what would otherwise require separate components, reducing overall manufacturing complexity despite the high pin density requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Quantity of substance

If minimum feature size is reduced to increase integration density, then component capacity is improved, but manufacturing precision requirements worsen

Engineering Contradiction:
Improveintegration densityVSAvoidfeature size precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent segments the manufacturing process into distinct modules: wafer-level processing for die fabrication, separate underfill application and curing steps, individual bump bond formation processes, and staged encapsulation. This segmentation allows each step to be optimized independently, maintaining manufacturing precision even as minimum feature sizes decrease to increase integration density.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11121070B2Integrated fan-out package
Publication Date: 2021.09.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11121070B2 patent drawing
  • US11121070B2 patent drawing
  • US11121070B2 patent drawing

AI summary

A device includes a package. The package includes a plurality of dies, an encapsulant encapsulating the plurality of dies, and a redistribution structure over the plurality of dies and the encapsulant. The device further includes first sockets bonded to a top surface of the redistribution structure and a rigid/flexible substrate bonded to the top surface of the redistribution structure. The rigid/flexible substrate includes a first rigid portion, a second rigid portion, and a flexible portion interposed between the first rigid portion and the second rigid portion. The device further includes second sockets bonded to the first rigid portion of the rigid/flexible substrate and connector modules bonded to the second rigid portion of the rigid/flexible substrate.