Rigid Interlayer Structure for Warpage-Controlled Chip Stacking
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Solution Overview
Problem
The scaling-down of semiconductor electronic devices leads to issues such as warpage, which affects electrical characteristics, quality, cost, and yield, and results in delamination and reduced reliability.
Innovation Solution
Incorporating a first rigid layer or metal layer between semiconductor chips to control warpage, enhancing bonding and reducing delamination risks through a method involving hybrid bonding and encapsulation with dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to meet application requirements, then device density and integration are improved, but warpage control deteriorates leading to delamination and reduced reliability
Solution Approach 1:
The patent applies local quality by implementing a multi-layer encapsulant structure with different material properties in specific regions. The first encapsulant has different mechanical properties than the second encapsulant, allowing localized stress management at the bonding interface between stacked semiconductor devices. This regional differentiation of material properties enables warpage control in the critical bonding area while maintaining overall device scaling.
Solution Approach 2:
The patent employs composite materials by combining multiple encapsulant layers with distinct material compositions. The first encapsulant may contain different filler content, resin systems, or cross-linking densities compared to the second encapsulant. This composite structure creates a gradient of mechanical properties that compensates for thermal expansion mismatches and stress accumulation during device operation, thereby controlling warpage while maintaining scaled-down dimensions.
2Adaptability or versatility
If multiple semiconductor chips are stacked to increase integration, then device functionality is improved, but bonding reliability deteriorates due to warpage and delamination
Solution Approach 1:
The patent implements local quality through a specialized encapsulant configuration where the first encapsulant directly surrounding the bonding interface has optimized mechanical properties for stress management. This localized encapsulant design provides enhanced support and stress distribution precisely where multiple chips are bonded together, improving bonding reliability without compromising the functionality of the stacked configuration.
Solution Approach 2:
The patent applies beforehand cushioning by incorporating the first encapsulant layer prior to or during the bonding process of stacked semiconductor chips. This encapsulant layer acts as a cushioning element that pre-compensates for thermal expansion differences and mechanical stresses that will occur during subsequent device operation, preventing delamination and maintaining bonding integrity throughout the device lifecycle.
Data Source
AI summary
The present application discloses an electronic device and a method for manufacturing the electronic device. The electronic device includes a first semiconductor chip encapsulated by a first encapsulant, a second semiconductor chip encapsulated by a second encapsulant and a first intermediate structure. The second semiconductor chip is disposed over and electrically connected to the first semiconductor chip. The first intermediate structure is interposed between the first semiconductor chip and the second semiconductor chip, and includes a first rigid layer. A periphery portion of the first rigid layer of the first intermediate structure vertically overlaps the first encapsulant and the second encapsulant, and is configured to control a warpage of the electronic device.