RIMRAM Array for In-Situ Neural Network Training
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Solution Overview
Problem
Current non-volatile memory arrays used in deep neural networks (DNNs) face challenges such as high energy consumption, slow training performance, and endurance issues, which limit their ability to perform online training and inference efficiently.
Innovation Solution
The implementation of a Resistance-In-Memory Random Access Memory (RIMRAM) array, where the non-volatility function is separated from the resistance tuning function, allowing for a single programming pulse to set the synaptic value, and using a real resistor with a pre-selected value to improve programming speed and energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If non-volatile flash memory cells are used for in-memory computing, then energy efficiency is improved by performing calculations inside memory, but training performance deteriorates due to slow and non-linear resistance tuning
Solution Approach 1:
The patent separates the non-volatile memory cell into two distinct functional components: a switching element (transistor) for digital control and a resistive element for analog weight storage. This segmentation allows the switching element to provide precise digital control signals for fast programming while the resistive element maintains the analog resistance value for energy-efficient in-memory computing operations.
Solution Approach 2:
The patent extracts the resistance tuning function from the non-volatile memory cell itself and implements it externally through a digital-to-analog converter (DAC). The DAC generates precise analog voltages that are applied to the memory cell during programming, enabling linear and fast resistance adjustment without the non-linearities inherent in direct memory cell programming.
2Measurement precision
If iterative programming algorithm is used to tune resistance values, then accuracy of synaptic resistances is improved, but training speed deteriorates due to slow programming process
Solution Approach 1:
The patent uses a digital-to-analog converter (DAC) to pre-calculate and generate the exact analog voltage required to achieve the desired resistance value in a single programming step. This preliminary calculation of the target resistance value eliminates the need for iterative programming and verification cycles, enabling direct programming to the precise target resistance.
Solution Approach 2:
The patent replaces the iterative mechanical-like programming process (apply voltage, measure resistance, adjust voltage, repeat) with a direct electronic control approach. The DAC electronically computes the required voltage based on the desired resistance and applies it directly to the memory cell, substituting the iterative feedback loop with a direct calculation and application method.
3Adaptability or versatility
If non-volatile flash memory cells are reused for multiple training cycles, then field-training capability is enabled, but endurance deteriorates causing retention issues
Solution Approach 1:
The patent employs a transistor as a disposable switching element that can be rapidly programmed and degraded without affecting the long-term retention of the weight information. The transistor handles the high-stress programming operations while the separate resistive element (which stores the actual weight) remains stable and retains its value over extended periods, effectively decoupling the short-lived programming stress from the long-lived weight storage.
4Reliability
If margins are added to counteract retention and endurance issues, then reliability of synaptic resistances is improved, but programming precision requirements worsen
Solution Approach 1:
The patent implements a feedback mechanism where the actual resistance value of the memory cell is measured during programming, and this measured value is fed back to the control system. The digital-to-analog converter (DAC) adjusts the programming voltage based on this feedback to achieve the exact target resistance value, eliminating the need for conservative margins and enabling precise programming even with process variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the number of programming pulses required, enhancing training speed and energy efficiency, while also mitigating retention and endurance issues, enabling DNN edge devices to perform both training and inference efficiently.
Implementation Method 1
Each non-volatile memory cell comprises a switch and a non-volatile memory coupled between one of the resistors and the switch
Implementation Method 2
coupled to a wordline and an input line. Each non-volatile memory cell is coupled to a different resistor such that each resistor has a different resistance value
Data Source
AI summary
An apparatus and system are described to provide an in-memory computing non-volatile flash memory cell array used in a neural network. Each cell includes a Resistive RAM memory (RRAM) and a physical resistor formed from a high resistive material. The RRAM is programmed to either an on or off state in which the resistance is respectively significantly less or more than the resistor to permit the RRAM to act as a switch and allow for in-situ training. Multi-bit RRAM cells contain multiple RRAMs, each of which is connected to a resistor having a different resistance and read using the same input line. The resistors are formed from the same material as the resistor in the analog-to-digital converter used to read the array.