Ring Buffer Cache Memory Management for Multi-Core Systems

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing technologies lack effective control over cache memory utilization, leading to inefficiencies and performance degradation due to limited cache space and competing processor cores.

Innovation Solution

A method utilizing a circular or ring data structure, referred to as a ring buffer, to manage and limit cache memory space. The ring buffer tracks production and consumption of data based on an eventual consistency model, dynamically adjusting its size based on utilization to optimize cache memory use.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If cache memory size is increased to improve data processing performance, then data transfer performance is improved, but memory cost and system complexity increase

Engineering Contradiction:
Improvedata transfer performanceVSAvoidcache memory size
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The ring buffer size is made dynamic rather than fixed, allowing it to adapt to changing workload conditions. The system monitors buffer utilization and adjusts the ring buffer size accordingly, enabling the cache memory to provide optimal performance for different data processing scenarios without permanently occupying excessive memory resources.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the parameter of buffer size from a static configuration to a dynamically adjustable parameter. By monitoring utilization metrics and adjusting the ring buffer size based on actual needs, the system optimizes cache memory usage to improve data transfer performance while preventing unnecessary memory consumption.

Inventive Principle:
Principle #35Parameter changes

2Loss of time

If ring buffer size is increased to reduce latency, then data processing speed is improved, but cache memory utilization efficiency decreases

Engineering Contradiction:
ImprovelatencyVSAvoidcache memory utilization efficiency
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The system implements feedback mechanisms that monitor ring buffer utilization and use this information to dynamically adjust buffer size. This closed-loop control ensures that the buffer size is optimized for both low latency and high cache utilization efficiency, preventing the trade-off from becoming a permanent contradiction by continuously adapting to actual workload conditions.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The ring buffer size transitions from a static parameter to a dynamic one that responds to utilization feedback. This allows the system to maintain low latency when needed while maximizing cache memory utilization efficiency under different workload conditions, resolving the contradiction through continuous adaptation.

Inventive Principle:
Principle #15Dynamics

3Productivity

If multiple processor cores access cache memory simultaneously, then processing throughput is improved, but cache memory conflicts and performance degradation increase

Engineering Contradiction:
Improveprocessing throughputVSAvoidcache memory performance stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The cache memory is segmented into multiple independent ring buffers, with each processor core assigned to specific buffer(s). This segmentation reduces conflicts between cores by providing dedicated access paths, allowing multiple cores to operate simultaneously with improved throughput while maintaining performance stability through reduced contention.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The ring buffer structure serves multiple functions: it acts as a dedicated cache for specific processor cores, a buffer for data transfer, and a mechanism for managing memory allocation. This multi-functionality allows the same structure to support multiple cores simultaneously while maintaining performance stability through its inherent allocation and management mechanisms.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12242387B2Systems and methods for managing memory utilization
Publication Date: 2025.03.04 SAMSUNG ELECTRONICS CO LTD
  • US12242387B2 patent drawing
  • US12242387B2 patent drawing
  • US12242387B2 patent drawing

AI summary

Systems and methods for managing memory are disclosed. In one embodiment, a first data structure is generated, where the first data structure is associated with one or more virtual addresses mapped to one or more physical addresses of the memory. A size of the first data structure is based on a characteristic of the memory. Data to be stored in the memory is received, and a virtual address of the one or more virtual addresses is identified based on the first data structure. The virtual address is mapped to a physical address, and the data is stored in the physical address. The first data structure is updated based on the storing of the data.