Ring Bus Memory System Scalable Expansion
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Solution Overview
Problem
Current memory systems face limitations in scalability and increased implementation costs due to the restrictive nature of low-speed serial interface standards, which limit the number of memory chips that can be connected to a single channel, making it difficult to expand memory capacity while maintaining cost-effectiveness.
Innovation Solution
A memory system configuration where a controller and multiple memory chips are connected in a ring shape using a loop bus, allowing for the sequential transmission of system clock and timing control signals, enabling flexible expansion of memory capacity without substantial changes to the hardware configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If low-speed serial interface standards are used to connect memory chips to a controller, then the interface is simple and cost-effective, but the number of memory chips that can be connected to a single channel is limited
Solution Approach 1:
The system segments the memory expansion capability by allowing multiple independent memory chips to be connected in series on a single channel, with each chip being individually addressable and controllable through the serial interface. This segmentation enables scalable memory capacity without requiring parallel interface channels for each chip.
Solution Approach 2:
The serial interface channel is designed with universal functionality to support multiple memory chips of potentially different types or capacities on the same channel. The controller can dynamically configure and manage different numbers of chips (e.g., 1-4 chips) on a single channel, making the interface adaptable to various memory expansion requirements without hardware changes.
2Adaptability or versatility
If the number of memory chips connected to a single channel is increased to expand memory capacity, then memory scalability improves, but implementation costs increase
Solution Approach 1:
Instead of expanding memory capacity by adding more parallel channels (horizontal dimension), the system expands by increasing the number of chips on a single serial channel (vertical dimension). This dimensional shift allows memory scalability while maintaining the cost benefits of a single channel architecture, as chips are added sequentially rather than requiring additional parallel interface resources.
Solution Approach 2:
The system enables dynamic parameter changes in the number of memory chips that can be accommodated on a single channel (configurable from 1 to 4 chips). This parameter flexibility allows the memory subsystem to be scaled according to specific application requirements without incurring the costs associated with fixed, high-capacity parallel interface configurations.
3Device complexity
If multiple memory chips are connected on a single serial channel, then hardware configuration remains simple, but timing control of multiple chips becomes complex
Solution Approach 1:
The controller acts as an intermediary that manages timing control for multiple memory chips on a single channel. It implements intelligent timing management and signal sequencing to coordinate operations across multiple chips, abstracting the timing complexity from the hardware interface level and providing simplified control through standardized command protocols.
Solution Approach 2:
The system performs preliminary timing configuration and synchronization setup before memory operations begin. The controller pre-configures timing parameters and establishes synchronization protocols for all chips on the channel, ensuring that subsequent memory operations can proceed without real-time timing coordination complexity.
Data Source
AI summary
According to one embodiment, there is provided a memory system including a controller, a plurality of memory chips, and a channel. The controller outputs a clock signal, a timing control signal and a data signal. Each of the plurality of memory chips includes at least a clock input terminal, a timing control input terminal, a timing control output terminal, a data input terminal and a data output terminal. The channel includes a loop bus which connects the controller and the plurality of memory chips in a ring shape. The controller is able to control operation timings of the memory chips by transmitting the clock signal and the timing control signal to the plurality of memory chips via the channel.