Ring Bus Verification Request Mechanism for Memory Write Integrity

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Solution Overview

Problem

In information processing systems with multiple apparatuses connected via a ring bus, there is a risk of data integrity issues due to incomplete memory write requests, where data access can occur before data is updated, leading to incorrect data being read from memory.

Innovation Solution

The system includes a processor that generates and transmits verification requests to ensure completion of memory write requests across multiple information processing apparatuses, using a verification register to confirm write completion responses, thereby ensuring that all memory write requests are completed before allowing data access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If verification requests are transmitted to ensure completion of memory write requests, then data integrity is improved, but transmission path traffic increases

Engineering Contradiction:
Improvedata integrityVSAvoidtransmission path traffic
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The system transmits verification requests in advance after write requests to proactively confirm memory write completion before data access occurs. This preliminary verification action ensures data integrity by preventing reads of unupdated data, while the verification requests are integrated into the existing ring bus protocol to minimize additional traffic overhead.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If verification requests are transmitted to ensure completion of memory write requests, then data integrity is improved, but processing time increases

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The verification request transmission is performed continuously as part of the normal write operation flow without interrupting the overall processing continuity. The verification process is embedded in the ring bus communication sequence, allowing write operations and verification to proceed in an integrated manner rather than as separate sequential steps, thereby minimizing additional processing time.

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If memory write completion is verified before data access, then data integrity is improved, but system complexity increases

Engineering Contradiction:
Improvedata integrityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The ring bus communication protocol serves multiple functions: it transmits both write requests and verification requests, carries data and status information, and coordinates between processors and memory systems. By making the ring bus a universal communication medium that handles verification as part of its standard protocol, the system avoids adding separate verification hardware or communication channels, thereby limiting the increase in system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10599347B2Information processing system, information processing apparatus, and method for controlling information processing system
Publication Date: 2020.03.24 FSAS TECH INC
  • US10599347B2 patent drawing
  • US10599347B2 patent drawing
  • US10599347B2 patent drawing

AI summary

An information processing system includes: a processor in one information processing apparatus among information processing apparatuses coupled via a ring bus corresponding to a closed-loop bus; and a first memory, wherein the processor: generate a verification request for verification of completion of a write request after issuing the write request to a second memory in the information processing apparatuses; transmit the verification request to a subsequent information processing apparatus; transmit, when a request from a preceding information processing apparatus is not a verification request, the request to the subsequent information processing apparatus; transmit, when the request is a verification request to another information processing apparatus, the verification request and a request to the first memory to the subsequent information processing apparatus in order of receiving; and execute, when the request is a verification request to the one information processing apparatus, processing and generate a response of completion of the processing.