Ring-Shaped Clock Signal Lines for Narrow Bezel Array Substrates
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Solution Overview
Problem
Existing array substrates face challenges in reducing signal delay in clock signal lines and achieving a narrow bezel in display devices, as thinning the clock signal lines to reduce bezel size increases RC delay due to increased overlap capacitance and resistance.
Innovation Solution
The array substrate design incorporates ring-shaped clock signal lines and multiple levels of clock signal lines to minimize overlap capacitance and resistance, with connection lines configured to reduce RC delay and implement a narrow bezel by arranging clock signal lines in concentric rings and connecting them via contact holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the clock signal lines are thinned to reduce bezel size, then the bezel width is reduced, but the RC delay increases due to increased resistance and overlap capacitance
Solution Approach 1:
The patent transitions from conventional linear clock signal lines to ring-shaped clock signal lines, adding a dimensional change that allows the lines to loop back and reduce overlap capacitance. This dimensional rearrangement enables the lines to maintain electrical performance while occupying less horizontal space, thereby reducing bezel width without increasing signal delay.
Solution Approach 2:
Multiple clock signal lines are arranged in concentric rings, with inner rings nested within outer rings. This nesting configuration reduces the horizontal space occupied by the clock signal lines, enabling narrower bezel width while maintaining signal integrity through reduced overlap capacitance between nested lines.
2Reliability
If multiple clock signal lines are arranged horizontally to reduce resistance, then the resistance decreases, but the bezel size increases
Solution Approach 1:
Instead of arranging multiple clock signal lines horizontally in a single layer, the patent stacks them vertically in concentric rings. This vertical arrangement in multiple dimensions reduces the horizontal footprint, allowing narrower bezel width while maintaining low resistance through multiple parallel signal paths.
Solution Approach 2:
Multiple clock signal lines are merged into a compact concentric ring structure where lines are positioned close together vertically. This merging reduces the overall horizontal space required while maintaining multiple signal paths for low resistance, achieving both signal quality and narrow bezel width.
3Object-generated harmful factors
If clock signal lines are made thinner to reduce overlap capacitance, then the capacitance decreases, but the resistance increases
Solution Approach 1:
The patent arranges multiple clock signal lines in concentric rings with vertical stacking, moving from a two-dimensional horizontal arrangement to a three-dimensional vertical arrangement. This dimensional change allows thinner lines with reduced overlap capacitance while maintaining low resistance through multiple parallel paths in different vertical layers.
Data Source
AI summary
An array substrate includes: a display area; a non-display area outside of the display area; a gate-in-panel (GIP) circuit in the non-display area; a plurality of clock signal lines in the non-display area and configured to transfer signals to the GIP circuit; and connection lines in the non-display area and configured to connect the plurality of clock signal lines to the GIP circuit. Each of the plurality of clock signal lines is a ring shaped line.