Ring Delay-Cell Clock Generator for Phase Skew Correction
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Solution Overview
Problem
Existing multi-phase clock signal generators require large circuit areas and high power consumption, and suffer from phase skew issues that are difficult to correct accurately, especially in high-speed applications.
Innovation Solution
A multi-phase clock signal generator using a ring phase shifting loop with controllable delay cells and a phase skew detecting circuit, which adjusts delay amounts via biasing voltage to correct phase skew and minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a quadrature oscillator is used to generate multi-phase clock signals, then the frequency can be controlled by voltage, but the circuit region becomes large and power consumption increases
Solution Approach 1:
The phase shifting function is segmented into multiple independent delay cells arranged in a ring structure. Each delay cell processes a portion of the phase shift, allowing the system to achieve multi-phase output without requiring a large quadrature oscillator circuit. This segmentation reduces the overall circuit area while maintaining frequency control capability.
Solution Approach 2:
The patent employs controllable delay cells with adjustable delay amounts through biasing voltage, creating a dynamic phase shifting system. This dynamic approach allows the ring phase shifting loop to adaptively generate multi-phase clock signals with different phases without requiring a fixed large-scale quadrature oscillator structure, thereby reducing circuit area.
2Measurement precision
If multiple delay lock loops are used to correct phase skew, then phase skew accuracy improves, but circuit size and power consumption increase
Solution Approach 1:
The patent combines the phase skew detection and correction functions into a single integrated ring phase shifting loop structure. The phase skew detecting circuit is merged with the biasing circuit that controls the delay cells, eliminating the need for separate multiple delay lock loops. This integration achieves phase skew correction while significantly reducing circuit size.
Solution Approach 2:
The patent implements a feedback mechanism where the phase skew detecting circuit monitors the phase differences of output clock signals and feeds this information to the biasing circuit. The biasing circuit adjusts the biasing voltage based on the detected phase skew, dynamically correcting the phase alignment. This feedback-based correction achieves high phase skew accuracy without requiring multiple independent delay lock loops.
3Adaptability or versatility
If analog multi-phase generator is used, then multi-phase clock signals can be generated, but power consumption becomes high and process portability decreases
Solution Approach 1:
The patent replaces traditional analog delay chain mechanisms with a digital-controlled ring phase shifting loop using controllable delay cells. The delay amounts are controlled through digital biasing voltage adjustment rather than analog component values. This substitution reduces power consumption and improves process portability while maintaining the ability to generate multi-phase clock signals.
Solution Approach 2:
The patent changes the control parameter from analog component values to digitally adjustable biasing voltage. By controlling the delay amounts through voltage parameters rather than fixed analog components, the system achieves lower power consumption and better process portability. The controllable delay cells respond to voltage changes, enabling flexible multi-phase generation with reduced energy consumption.
4Adaptability or versatility
If quadrature oscillator frequency is controlled by voltage, then frequency adjustment is possible, but sensitivity to supply voltage noise increases
Solution Approach 1:
The patent introduces a phase skew detecting circuit as an intermediary between the voltage control and the delay cells. This intermediary monitors the actual phase output and adjusts the biasing voltage accordingly, compensating for supply voltage noise effects. The feedback mechanism acts as a mediator that isolates the frequency adjustment function from noise sensitivity, maintaining reliability while preserving frequency adaptability.
Data Source
AI summary
A multi-phase clock signal generator, comprising: a ring phase shifting loop, including a plurality of controllable delay cells, for generating output clock signals having different phases via the controllable delay cells according to a input clock signal, wherein delay amount of the controllable delay cells are determined by a biasing voltage; a phase skew detecting circuit, for computing phase differences of the output clock signals to generate a phase skew detecting signal; and a biasing circuit, for providing the biasing voltage according to the phase skew detecting signal. The above-mentioned ring phase shifting loop can operate independently from the multi-phase clock signal generator, without receiving the biasing voltage, for phase-shifting a input clock signal to generate output clock signals with different phases, wherein the output clock signals are respectively output at different output terminals respectively located between the phase shifting units.