Ring Serial Communication Clock Recovery With Fractional Oversampling
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Solution Overview
Problem
Asynchronous serial communication systems face challenges in maintaining accurate clock synchronization between devices, leading to data errors due to frequency mismatches, especially in applications like battery management systems where clock frequency tolerances are critical and traditional oscillators are costly or inefficient.
Innovation Solution
Implementing a fractional rate multiplier in receiving devices to generate an oversampling clock that matches the baud rate by detecting a predetermined bit sequence and adjusting the denominator, allowing for improved clock synchronization and reduced sampling errors across a wide range of baud rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional crystal oscillators are used to match transmit and receive clocks, then clock frequency stability is improved, but cost and power consumption increase significantly
Solution Approach 1:
The patent changes the parameter of clock synchronization from using fixed-frequency crystal oscillators to using a fractional rate multiplier that can dynamically adjust its output frequency. The fractional rate multiplier uses a phase-locked loop to lock onto the baud rate signal and generates an oversampling clock with exactly 16 samples per bit, adapting to different baud rates without requiring expensive crystal oscillators for each frequency.
2Reliability
If crystal oscillators are used to match transmit and receive clocks, then clock frequency stability is improved, but device cost increases
Solution Approach 1:
The patent changes the parameter of clock synchronization from using fixed-frequency crystal oscillators to using a fractional rate multiplier that can dynamically adjust its output frequency. The fractional rate multiplier uses a phase-locked loop to lock onto the baud rate signal and generates an oversampling clock with exactly 16 samples per bit, adapting to different baud rates without requiring expensive crystal oscillators for each frequency.
3Ease of manufacture
If RC oscillators are used instead of crystal oscillators, then cost and power consumption are reduced, but frequency stability deteriorates due to sensitivity to process, voltage, and temperature variations
Solution Approach 1:
The patent implements feedback through a phase-locked loop in the fractional rate multiplier. The PLL continuously monitors the baud rate signal and adjusts the oversampling clock frequency to maintain exactly 16 samples per bit. This feedback mechanism compensates for frequency drift caused by process, voltage, and temperature variations, achieving frequency stability without requiring expensive crystal oscillators.
4Device complexity
If integer dividers are used to generate sampling clock from system clock, then device complexity is reduced, but sampling accuracy deteriorates due to inability to achieve exact 16x baud rate multiplication
Solution Approach 1:
The patent changes the parameter of clock generation from using simple integer dividers to using a fractional rate multiplier with a phase-locked loop. The fractional rate multiplier can achieve exact 16x multiplication of the baud rate by using fractional division ratios, providing precisely timed sampling clocks that maximize immunity to noise and minimize sampling errors, while still maintaining reasonable device complexity.
Data Source
Figure 1A
Figure 1B
Figure 2~3
AI summary
Systems and methods are disclosed which relate to serial communication in a ring network. The method comprises receiving, at a slave device, a bit sequence from a master device on the ring network, the bit sequence being encoded using bi-frequency encoding; synchronizing an oversampling clock to a baud rate of the received bit sequence; parsing the bit sequence to determine that the bit sequence is addressed to the slave device and that the master device is requesting data back from the slave; filling in one of a plurality of placeholder bits in the bit sequence by inverting the bit sequence midway through the bit time; and forwarding the inverted bit sequence to a subsequent slave device on the ring network, wherein the start of each bit in the bit sequence is signaled by the master device inverting the bit sequence a first time to represent a 0 and a second time to represent a 1.