Ring Oscillator DCO with Dual DAC Tuning for Speed and Resolution
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Solution Overview
Problem
Designing a high-speed, high-resolution ring-oscillator based digitally-controlled oscillator (DCO) is challenging due to the need for a complex tuning network that balances frequency granularity and speed, while also meeting low-noise requirements, which is difficult to achieve with existing technologies.
Innovation Solution
A DCO design comprising a ring oscillator with a low-speed DAC for coarse control, a varactor array for capacitive load adjustment, and a high-speed DAC array for fine control, allowing for separate optimization of speed and resolution through a dual-control word approach.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a complex tuning network is used to achieve high resolution, then the frequency tuning granularity is improved, but the circuit speed deteriorates
Solution Approach 1:
The patent divides the single control word into two separate control words: a coarse control word (WC) for integer frequency steps and a fine control word (WF) for fractional frequency steps. This segmentation allows the tuning network to be split into two independent paths, enabling high resolution through the fine control path without compromising the speed of the coarse control path.
Solution Approach 2:
The patent introduces an intermediary mechanism where the fine control word adjusts the oscillation frequency based on feedback from a timing error detector. This intermediary fine-tuning stage allows precise frequency adjustment without requiring the entire tuning network to be complex and slow, as only the fine control path needs high granularity.
2Adaptability or versatility
If a highly complex tuning network is used to cover large PVT variation spread, then the frequency tuning range is improved, but the circuit complexity increases
Solution Approach 1:
The patent segments the frequency tuning function into two independent control mechanisms: coarse control for large frequency shifts (covering PVT variations) and fine control for small frequency adjustments. This allows the tuning network to achieve wide tuning range without requiring a single overly complex structure, as each segment can be optimized independently.
Solution Approach 2:
The patent implements dynamic control where the coarse and fine control words work together adaptively. The coarse control provides the baseline frequency setting while the fine control dynamically adjusts based on timing error feedback, allowing the system to cover large PVT variations without requiring the entire network to be maximally complex at all times.
3Speed
If a high-speed circuit is designed to reduce delay time, then the oscillation frequency response speed is improved, but the noise level increases
Solution Approach 1:
The patent segments the control function into two parts: a fast coarse control path that responds quickly to frequency changes and a slower fine control path that makes precise adjustments. This segmentation allows the critical fast response path to operate at high speed without excessive noise, while the fine control path can use lower-speed, lower-noise circuitry for its less time-critical adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables a high-speed, high-resolution DCO with low noise by using a low-speed DAC for initial frequency alignment and a high-speed DAC for closed-loop adjustments, effectively addressing the complexity and noise issues in existing designs.
Implementation Method 1
a varactor array configured to provide a capacitive load to said inter-stage node in accordance with a control voltage array
Data Source
AI summary
A method comprises: using a plurality of gain stages cascaded in a ring topology to form a ring oscillator configured to output an oscillation signal; controlling a supply voltage of said ring oscillator using a low-speed DAC (digital-to-analog converter) in accordance with a coarse control word; providing a capacitive load at an inter-stage node of said ring oscillator using a varactor array controlled by a control voltage array; establishing said control voltage array using a high-speed DAC array in accordance with a fine control word; adjusting the coarse control word upon a start-up to make an oscillation frequency of said oscillation signal approximately equal to target value; and adjusting the fine control word in a closed loop manner in accordance with a detection of a timing error of said oscillation signal.