Ring Encoder Cycle Counting for Real-Time Synthesizer Linearity Measurement

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Solution Overview

Problem

Conventional methods for monitoring frequency error and linearity in high-frequency clock outputs from frequency synthesizers, such as those used in automotive radar systems, are inefficient due to the slow speed of binary counters, requiring external equipment for offline measurements and lacking real-time capabilities.

Innovation Solution

The implementation of a ring encoder and binary counter module on a semiconductor chip, which encodes the least significant bits and counts the most significant bits, combined with a frequency estimator using a reference clock for error correction and differentiation, enables real-time monitoring and high-resolution linearity measurement of the clock output frequency without external equipment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a binary counter is used to count clock cycles for frequency monitoring, then the counting function is implemented, but the speed is too slow for real-time monitoring of high-frequency clock outputs

Engineering Contradiction:
Improvecounting speedVSAvoidfrequency monitoring accuracy
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent divides the clock cycle counting function into two separate components: a ring encoder that captures least significant bits (LSBs) at high speed, and a binary counter that counts most significant bits (MSBs). This segmentation allows each component to operate optimally - the ring encoder handles high-frequency sampling while the binary counter provides accurate accumulation, together achieving real-time frequency monitoring capability.

Inventive Principle:
Principle #1Segmentation

2Productivity

If down-sampling of the clock signal is performed to monitor frequency error, then the monitoring becomes feasible, but real-time capabilities and high-resolution linearity measurement are lost

Engineering Contradiction:
Improvemonitoring capabilityVSAvoidlinearity measurement resolution
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The ring encoder performs preliminary action by capturing and encoding the LSBs of clock cycles before the binary counter accumulates the MSBs. This preliminary encoding of high-frequency information allows the system to maintain real-time monitoring capability and high-resolution linearity measurement without requiring down-sampling, as the fine temporal details are preserved in the ring encoder output.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If external equipment is used for offline frequency linearity measurement, then measurement capability is achieved, but real-time monitoring and continuous safety assurance are not available

Engineering Contradiction:
Improvefrequency linearity measurementVSAvoidreal-time monitoring capability
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent implements self-service by integrating both the ring encoder and binary counter on a single semiconductor chip, enabling the system to perform its own frequency monitoring and linearity measurement without requiring external equipment. This self-contained architecture provides continuous real-time monitoring capability while maintaining measurement precision, allowing the system to ensure its own safety and performance autonomously.

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP3262761B1Frequency synthesizer output cycle counter including ring encoder
Publication Date: 2020.06.10 TEXAS INSTRUMENTS INC
  • EP3262761B1 patent drawingFigure 1A
  • EP3262761B1 patent drawingFigure 1B
  • EP3262761B1 patent drawingFigure 2

AI summary

In described examples of a method of frequency estimation, a clock output from a frequency synthesizer (110) is received at an input of a ring encoder (121). The ring encoder (121) generates outputs, including a ring encoder output clock and an encoded output that represents LSBs of a clock cycle count of the clock output. A binary counter (122) is run using the ring encoder output clock, which provides an output count that represents MSBs of the clock cycle count. Using a frequency estimator (123) that is provided a reference clock, the encoded output is sampled to provide a sampled encoded output, and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output, and the corrected sampled encoded output and sampled output count are combined, which is used for estimating an instantaneous or average frequency of the clock output.