Ring-Gate Dynamic Comparator for Faster Low-Delta Voltage Settling
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Solution Overview
Problem
Dynamic comparators, particularly edge-tracking type comparators, suffer from increased stabilization time and power consumption as the difference between compared voltages decreases, leading to inefficiencies in applications like successive approximation analog-to-digital converters.
Innovation Solution
A dynamic comparator design with a ring of logic gates, where each gate is controllable and biased differently to prevent switching based on the state of associated gates, reducing settling time and power consumption by blocking the propagation of slower edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If edge-tracking type dynamic comparator is used, then comparison speed is improved, but power consumption increases and stabilization time increases as voltage difference decreases
Solution Approach 1:
The patent implements dynamic biasing of logic gates within a ring oscillator structure, where bias conditions change based on the comparison process state. This dynamic adjustment allows the comparator to operate at high speed during active comparison while reducing power consumption during stabilization, resolving the contradiction between speed and power usage.
Solution Approach 2:
The ring oscillator structure with controllable gates creates periodic oscillation that enables the comparator to achieve rapid stabilization through oscillatory convergence rather than gradual settling. This periodic action allows fast comparison speed while limiting overall power consumption through controlled oscillation cycles.
2Speed
If edge-tracking type dynamic comparator is used, then comparison speed is improved, but stabilization time increases as voltage difference decreases
Solution Approach 1:
The dynamic biasing mechanism adjusts gate thresholds during the comparison process, enabling the ring oscillator to rapidly converge to a stable state. This dynamic adaptation allows the system to maintain high comparison speed while reducing stabilization time, even for small voltage differences.
Solution Approach 2:
The ring oscillator structure provides inherent feedback where the output of each logic gate feeds back to control the next gate's switching behavior. This feedback mechanism accelerates stabilization by creating self-correcting oscillations that quickly dampen to a stable final state, reducing stabilization time without sacrificing comparison speed.
Data Source
Figure 1~2
Figure 3~5
AI summary
This description relates to a comparator (2) comprising a ring of gates (110A, 110B, 110A', 110B', 106, 108) in series, in which: each gate implements an inverting function between a first input (100) and an output (102) of the gate; at least one (110A', 110B') gate is controllable and is associated with another gate; each controllable gate (110A', 110B') includes a control input (116) connected to the output (102) of said associated gate, and prevents its output (102) from switching to a high state if its control input (116) is high, and to a low state otherwise; and the control input (116) of each controllable door (110A', 110B') receives the output (102) of said associated door if an even number of doors separates these two doors, and receives the complement of said output otherwise.