Ring-Gate Semiconductor Layout for High-Voltage Isolation Density
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Solution Overview
Problem
Existing high voltage semiconductor devices face limitations in achieving high breakdown voltage and efficient integration due to issues with junction isolation and rectangular nEDMOS designs, which lead to increased chip size and concentrated electric fields at corners.
Innovation Solution
A semiconductor device with a ring-shaped gate electrode and deep trench isolation regions, featuring a buried oxide film and impurity layers, allows for a controllable channel length and improved breakdown voltage by reducing chip area and minimizing electric field concentration through specific curvature designs and isolation structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If junction isolation is used in a bulk wafer, then isolation is achieved, but the chip size increases due to the area occupied by the junction isolation region
Solution Approach 1:
The patent transitions from planar junction isolation to three-dimensional deep trench isolation. The isolation structure extends vertically into the substrate with trench depth exceeding 10 micrometers, utilizing the depth dimension to achieve isolation without increasing lateral chip area. This vertical isolation approach maintains electrical separation while preserving chip real estate.
Solution Approach 2:
The patent extracts the isolation function from the planar junction region and implements it through separate deep trench structures. The trenches are filled with insulating material and extend deep into the substrate, removing the need for large lateral isolation regions while maintaining effective electrical isolation between adjacent devices.
2Device complexity
If a rectangular typed nEDMOS is used, then device structure is simple, but high breakdown voltage cannot be obtained because electric fields can be concentrated at each corner
Solution Approach 1:
The patent replaces rectangular gate electrode corners with rounded or curved profiles. The gate electrode features rounded corners with radii of curvature between 0.5 to 2 micrometers, which redistributes the electric field density and eliminates concentration at sharp corners. This curvature modification maintains structural simplicity while achieving high breakdown voltage characteristics.
Solution Approach 2:
The patent applies different geometric characteristics to different regions of the gate electrode. While the overall structure remains simple and rectangular, the corner regions are locally modified with rounded profiles to specifically address electric field concentration issues, while the central regions maintain their original simple geometry.
3Productivity
If continuous scale down is implemented, then integration density increases, but sufficient operating characteristics become difficult to secure
Solution Approach 1:
The patent utilizes the vertical dimension through deep trench isolation structures extending 10 micrometers or more into the substrate. This three-dimensional isolation enables closer lateral spacing of devices (increasing integration density) while maintaining adequate electrical isolation and operating characteristics through the depth dimension.
Solution Approach 2:
The patent segments the isolation function into multiple deep trench structures that can be independently optimized. Each trench provides localized isolation, allowing devices to be closely spaced while maintaining sufficient isolation performance. This segmented approach enables continuous scale down while preserving operating characteristics.
Data Source
AI summary
A semiconductor device includes a ring-shaped gate electrode having an opening area disposed on a substrate, a source region and a bulk tap region disposed in the opening area, a well region disposed to overlap the ring-shaped gate electrode, a drift region disposed to be in contact with the well region, a first insulating isolation region disposed, on the drift region, to partially overlap the gate electrode, a second insulating isolation region enclosing the bulk tap region, a drain region disposed to be spaced apart from the ring-shaped gate electrode, and a deep trench isolation region disposed adjacent to the drain region.