Ring-Based Matching Network for On-Chip Impedance Compensation
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Solution Overview
Problem
Advanced CMOS technologies combined with advanced packaging methodologies face challenges in achieving impedance matching at on-chip transitions due to capacitive contributions from packaging connections like solder bumps and pillars, leading to signal degradation.
Innovation Solution
Implementing ring-based matching networks that include capacitively coupled rings to on-chip pads, coupled to ground through on-chip inductors, with programmable switches to provide impedance compensation and reduce insertion losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If advanced packaging connections (solder bumps, pillars) are used to connect chips, then connection density and integration are improved, but capacitive contributions increase causing impedance mismatch and signal degradation
Solution Approach 1:
The patent introduces an intermediary impedance compensation network between the packaging connection and the on-chip circuit. This network includes a compensation capacitor connected to ground that acts as a mediator to cancel the capacitive effect of the packaging connection, thereby restoring proper impedance matching without changing the packaging structure itself.
Solution Approach 2:
The patent modifies the electrical parameters of the signal path by adding compensation capacitors with specific values (e.g., 0.5pF to 2pF) to counterbalance the capacitive contribution of packaging connections. This parameter adjustment allows the system to maintain 50-ohm impedance matching despite the presence of high-density packaging connections.
2Ease of manufacture
If traditional impedance matching methods are used at on-chip transitions, then manufacturing simplicity is maintained, but impedance matching accuracy deteriorates due to capacitive contributions from packaging
Solution Approach 1:
The impedance compensation network is fully integrated into the chip fabrication process using standard CMOS工艺的 capacitors and resistors. The compensation capacitors are formed using the same metal layers and fabrication steps as the rest of the circuit, requiring no additional manufacturing steps or specialized processes.
Solution Approach 2:
The patent uses standard on-chip passive components (capacitors, resistors) that serve dual purposes: they perform their primary circuit function while simultaneously providing impedance compensation. This multi-functionality allows the same manufacturing process to produce both the functional circuit and the impedance matching network.
3Reliability
If compensation networks are added to offset capacitive contributions, then impedance matching is improved, but device complexity increases
Solution Approach 1:
The patent divides the impedance compensation function into discrete, modular compensation capacitors that can be independently sized and positioned. Each compensation capacitor is associated with a specific packaging connection, allowing the total capacitive effect to be cancelled through systematic segmentation of the compensation task across multiple locations.
Solution Approach 2:
The patent moves the impedance compensation function from the horizontal plane (on-chip signal path) to the vertical dimension by connecting compensation capacitors to ground. This dimensional transition allows the compensation network to operate in parallel with the signal path without interfering with the primary signal flow, thereby reducing complexity.
4Reliability
If precise impedance matching is achieved, then signal quality is improved, but insertion losses increase due to mismatch compensation requirements
Solution Approach 1:
The patent applies preliminary anti-action by pre-compensating for the capacitive effect of packaging connections through carefully designed compensation capacitors. This pre-compensation prevents impedance mismatch before it can cause signal reflections and energy loss, thereby maintaining signal quality without incurring additional insertion losses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ring-based matching networks achieve impedance matching within +/- 20% of the characteristic impedance with insertion losses reduced by >20 dB, effectively compensating for capacitive and inductive contributions, and allowing for tuning during industrial testing.
Implementation Method 1
ring-based matching networks that include capacitively coupled rings to on-chip pads
Implementation Method 2
coupled to ground through on-chip inductors
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
An electronic device may include semiconductor wafer including a semiconductor substrate and multiple layers on the semiconductor substrate. The multiple layers may include metal layers and dielectric layers forming a circuit and an on-chip pad configured to receive a signal. The device may include a ring-based matching network and a wire trace. The network may include one or more rings arranged within the multiple layers and extending around the on-chip pad to provide a selected impedance compensation to the received signal to produce a compensated signal. Each ring may have a selected width and a selected spacing relative to one or more of the on-chip pad or another ring. The wire trace may be configured to couple the on-chip pad to the circuit to provide the compensated signal. In some embodiments, one of the rings may be connected to or may be capacitively coupled to the on-chip pad.