Ring Oscillator Clock Equalization for Memory Phase Mismatch
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Solution Overview
Problem
Semiconductor memory devices experience phase-to-phase mismatching, duty cycle variation, and jitter in multi-phase clock circuits, leading to data distortion, read errors, and write errors, especially at high clock frequencies.
Innovation Solution
A ring oscillator circuit is employed to equalize clock parameters across multiple clock signals, reducing phase-to-phase delay mismatch, duty cycle variation, and jitter without additional duty-cycle correction or delay trimming circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-phase clock circuits are used to increase data rate, then productivity is improved, but phase-to-phase mismatching and jitter increase causing reliability deterioration
Solution Approach 1:
The patent combines multiple clock signals (first and second clock signals with different phases) into a single averaged clock signal by summing them together. This merging approach averages out the phase variations and jitter of individual clock signals, producing a more stable clock signal that maintains the high data rate capability of multi-phase clocking while reducing phase-to-phase mismatching and reliability issues
2Reliability
If additional duty-cycle correction or delay trimming circuitry is added to reduce phase mismatch, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent makes the clock circuit nodes multi-functional by having them perform both normal clock signal distribution and phase averaging functions simultaneously. The same circuit nodes that distribute clock signals also sum the clock signals to create the averaged clock signal, eliminating the need for separate duty-cycle correction or delay trimming circuitry while maintaining reliability improvements
3Productivity
If clock frequency is increased to improve data rate, then productivity is improved, but phase-to-phase mismatching and jitter worsen
Solution Approach 1:
The patent utilizes the periodic nature of clock signals by summing multiple periodic clock signals with different phases over time. This periodic averaging process systematically reduces phase-to-phase delay mismatch and jitter while maintaining the high clock frequency needed for improved data rate, as the periodic summation naturally filters out timing variations
Data Source
AI summary
A memory device may include memory cell array a clock circuit configured to generate a plurality of clock signals for access operations associated with the memory cell array. The clock circuit may include a ring oscillator circuit that is configured to equalize phase distortions of the plurality of clock signals.