Ring Oscillator Clock Detection for Duty Cycle and Phase Error

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing technologies fail to accurately maintain the duty cycle ratio and phase difference of multi-phase clocks in integrated circuits due to noise, leading to deviations from ideal values.

Innovation Solution

A duty cycle detector and phase difference detector are implemented using ring oscillators with odd numbers of inverters and frequency comparators, which generate periodic signals based on clock values to compare frequencies and determine duty cycle and phase difference signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multi-phase clocks are used to transfer data at high rates, then data transfer capability is improved, but phase difference and duty cycle ratio deviate from ideal values due to noise

Engineering Contradiction:
Improvedata transfer rateVSAvoidphase difference and duty cycle ratio accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The invention divides the detection function into separate dedicated circuits: a duty cycle detector that measures high/low pulse width ratios and a phase difference detector that measures phase offsets between clocks. This segmentation allows each detector to be optimized for its specific measurement task, improving accuracy without compromising data transfer capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention introduces intermediary detection circuits (duty cycle detector and phase difference detector) that measure clock parameters and provide correction signals. These intermediaries enable the system to monitor and correct deviations caused by noise, maintaining measurement precision while preserving high data transfer rates.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If duty cycle ratio and phase difference are maintained at ideal values, then clock performance is optimized, but detection accuracy is insufficient under noise conditions

Engineering Contradiction:
Improveclock performance stabilityVSAvoiddetection accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The invention implements feedback mechanisms where the duty cycle detector and phase difference detector continuously monitor clock parameters and generate correction signals. These feedback signals enable real-time adjustment to maintain ideal duty cycle ratios and phase differences, improving reliability under noise conditions through continuous measurement and correction.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The invention replaces simple mechanical clock distribution with an intelligent system incorporating electronic detection circuits. The duty cycle detector and phase difference detector use electronic measurement and signal processing to achieve high detection accuracy, substituting passive mechanical systems with active electronic measurement systems that can compensate for noise.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10361692B2Duty cycle detector and phase difference detector
Publication Date: 2019.07.23 SK HYNIX INC
  • US10361692B2 patent drawing
  • US10361692B2 patent drawing
  • US10361692B2 patent drawing

AI summary

A duty cycle detector includes a first ring oscillator suitable for including an odd number of first inverters and generating a first periodic signal by using the first inverters, at least one inverter among the first inverters being enabled during a time interval when a clock has a first value, a second ring oscillator including an odd number of second inverters and suitable for generating a second periodic signal using the second inverters, at least one inverter among the second inverters being enabled during a time interval when the clock has a second value. The duty cycle detector further includes a frequency comparator suitable for comparing a frequency of the first periodic signal with a frequency of the second periodic signal and generating a duty cycle detection signal of the clock.