Ring Oscillator Clock Taps for Non-Overlapping Multi-Phase Clocks
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Solution Overview
Problem
Existing ring oscillators in electronic systems face challenges in generating multi-phase, multi-duty cycle, non-overlapping clocks while managing current consumption and minimizing current draw on power frames, as they often require faster clocks and are not adaptive to process, voltage, and temperature variations.
Innovation Solution
An integrated ring oscillator clock generator with a series of inverting stages and a combinational logic stage, tapped at multiple locations to generate multi-phase, multi-duty cycle, non-overlapping clocks, using delay circuitry such as inverters, buffers, transistors, resistors, and capacitors, and logic gates like AND, NAND, OR, and NOR to manage current consumption and adapt to variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If a ring oscillator uses a higher number of gates to increase delay, then the available delay increases, but the operating frequency decreases
Solution Approach 1:
The ring oscillator is segmented into multiple independent delay stages, each contributing to the total delay. By dividing the oscillator into N stages with individual delay elements (inverters, buffers, transistors, resistors, capacitors), the design achieves cumulative delay while maintaining controllable frequency through the staged architecture.
Solution Approach 2:
The oscillator incorporates adaptive delay control mechanisms that allow dynamic adjustment of delay characteristics. The delay elements can be tuned or adapted based on process, voltage, and temperature variations, enabling the system to maintain optimal performance across different operating conditions while balancing delay and frequency requirements.
2Adaptability or versatility
If existing ring oscillators generate multi-phase clocks using faster clocks, then the clock generation capability improves, but the current draw on power frame increases
Solution Approach 1:
Multiple clock phases are generated by tapping intermediate signals from the ring oscillator stages and combining them through combinational logic circuits. Instead of using separate faster oscillators for each phase, the design merges the functionality into a single oscillator structure, reducing overall current consumption while maintaining multi-phase output capability.
Solution Approach 2:
The ring oscillator naturally produces periodic signals at different stages, which are tapped and combined to create multi-phase clocks. This periodic action at intermediate points allows derivation of multiple clock phases from a single fundamental oscillation, avoiding the need for additional higher-frequency oscillators and their associated current draw.
3Device complexity
If existing ring oscillators are not adaptive to process, voltage, and temperature variations, then the circuit complexity is reduced, but the clock signal integrity deteriorates
Solution Approach 1:
The ring oscillator incorporates feedback mechanisms that monitor and adjust delay characteristics based on operating conditions. The oscillation signal feeds back through the delay stages, allowing the circuit to self-regulate and maintain stable frequency and signal integrity despite process, voltage, and temperature variations without requiring complex external control circuits.
Solution Approach 2:
The oscillator design includes delay elements with adjustable parameters (such as transistor sizes, resistor values, capacitor values) that can be tuned to compensate for PVT variations. By changing these physical parameters during design or operation, the circuit maintains consistent clock signal integrity across different operating conditions while keeping the overall architecture relatively simple.
Data Source
AI summary
A clock generator includes a series of inverting stages; and at least one combinational logic stage. The series of inverting stages is tapped at two or more locations along the series of inverting stages to provide intermediary outputs. A combinational logic stage of the at least one combinational logic stage is coupled to receive two or more of the intermediary outputs and generate a clock signal. Multi-phase, multi-duty cycle, non-overlapping clock signals can be generated by the clock generator based on different combinations of intermediary outputs. The clock signals can be provided to a switching network.