Ring Oscillator Delay Line for Compact, Voltage-Stable Timing
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Solution Overview
Problem
Existing programmable delay lines face challenges in achieving a small integrated circuit footprint, matching rise and fall transitions, and maintaining delay sensitivity independence from supply voltage variations, while providing a large range of programmable delays.
Innovation Solution
A ring oscillator-based programmable delay line is implemented, comprising a pulse generator, ring oscillator, counter, and gating device, which generates a pulse and clock to adjust the delay of an input signal, ensuring matching rise and fall transitions and minimizing sensitivity to supply voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a traditional programmable delay line is implemented, then it can provide programmable delay functionality, but it occupies a large integrated circuit footprint
Solution Approach 1:
The patent employs a ring oscillator whose oscillation period can be dynamically adjusted by changing the number of active inverters in the feedback loop. This dynamic reconfiguration allows the delay line to achieve multiple delay values within a compact area, resolving the contradiction between small footprint and large programmable delay range.
Solution Approach 2:
The invention changes the operational parameters of the ring oscillator by varying the effective number of inverters participating in the oscillation cycle. This parameter change enables continuous adjustment of the oscillation period and thus the delay, providing a compact yet versatile programmable delay solution.
2Adaptability or versatility
If a programmable delay line is designed to provide large delay range, then it achieves versatility, but the delay matching between rise and fall transitions deteriorates
Solution Approach 1:
The patent introduces asymmetric control mechanisms for rise and fall transitions by using separate enable signals (EN_R and EN_F) and complementary inverter configurations. This asymmetric design allows independent optimization of rise and fall delay paths, achieving precise delay matching even across large programmable ranges.
Solution Approach 2:
The ring oscillator's inherent feedback loop through the chain of inverters provides automatic stabilization of the oscillation waveform. This feedback mechanism ensures that both rising and falling edges maintain consistent timing characteristics, improving delay matching while preserving the programmable delay range.
3Adaptability or versatility
If the programmable delay line is reconfigured to provide greater delays, then adaptability improves, but the device complexity increases
Solution Approach 1:
The delay line is segmented into multiple identical inverter stages that can be selectively activated. Each stage is a simple, repeatable unit, and the overall delay is controlled by enabling or disabling specific segments through programmable logic. This segmentation achieves high adaptability while keeping individual components simple and the overall system manageable.
Data Source
AI summary
A programmable delay line includes a pulse generator configured to generate a pulse in response to a transition of an input signal; an oscillator configured to generate a clock in response to the pulse; a counter configured to change a current count from a first value towards a second value in response to periods of the clock; and a gating device configured to output the transition of the input signal to generate an output signal in response to the current count reaching the second value. The delay of the input signal is a function of the difference between the first value and the second value. The delay line may be used in different applications, such as a dynamic variation monitor (DVM) configured to detect supply voltage droop. The DVM may be in an adaptive clock distribution (ACD) to reduce the clock frequency for a datapath in response to a droop.