Ring-Oscillator DLL for Accurate Phase Shift and Duty Cycle Correction
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Solution Overview
Problem
Existing delay locked loops (DLLs) face challenges in achieving accurate phase shift and duty cycle correction due to mismatch between delay lines, leading to increased design complexity, size, and power consumption, especially in semiconductor memory devices where precise timing is critical.
Innovation Solution
A DLL design incorporating a ring oscillator and frequency dividers to synchronize feedback clock signals with the reference clock, allowing for accurate phase shift and duty cycle correction without a separate duty cycle correction block, using a single delay line to reduce size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple delay lines are used to generate phase-shifted clocks, then phase shift accuracy is improved, but device complexity and area increase
Solution Approach 1:
The patent merges multiple delay lines into a single delay line structure. Instead of using separate delay lines for each phase shift (90°, 180°, 270°, 360°), the invention uses one delay line with a feedback mechanism that recycles the delay element multiple times to generate all required phase-shifted clocks, thereby reducing device complexity and area while maintaining phase shift accuracy
Solution Approach 2:
The patent introduces a feedback mechanism where the output of the delay line is fed back to its input after passing through a phase detector. This feedback loop allows the single delay line to be reused multiple times to generate different phase shifts, enabling accurate phase shifting without requiring multiple independent delay lines
2Measurement precision
If a separate duty cycle correction circuit is added to the DLL, then duty cycle correction accuracy is improved, but device area and power consumption increase
Solution Approach 1:
The patent combines the duty cycle correction function with the existing phase shift generation circuitry. The same delay line and feedback mechanism used for phase shifting are also utilized for duty cycle correction, eliminating the need for a separate duty cycle correction circuit and thereby reducing device area and power consumption
Solution Approach 2:
The delay line and feedback mechanism are designed to perform multiple functions: both phase shifting and duty cycle correction. This multi-functional design allows a single circuit structure to achieve both objectives, reducing the overall DLL area and power consumption compared to having separate dedicated circuits for each function
3Measurement precision
If multiple delay lines with independent controllers are used, then phase shift accuracy is improved, but design complexity and power consumption increase
Solution Approach 1:
The patent merges multiple independently controlled delay lines into a single delay line with a unified control mechanism. The feedback loop allows this single delay line to generate multiple phase shifts, eliminating the need for multiple independent controllers and reducing power consumption while maintaining phase shift accuracy
Solution Approach 2:
The single delay line is designed to be universally applicable for generating all required phase shifts (90°, 180°, 270°, 360°) through the feedback mechanism, replacing multiple specialized delay lines. This universal design reduces the total number of controllers needed and thereby reduces overall power consumption
Data Source
AI summary
Provided is a delay locked loop (DLL) including a ring oscillator (RO) including a delay line to delay a reference clock signal and generate a delayed clock signal, wherein the RO circulates, through the delay line, a feedback clock signal corresponding to the delayed clock signal to synchronize N cycles of the feedback clock signal with a cycle of the reference clock signal (where N is an integer number equal to or larger than 2); and a first frequency divider dividing the frequency of the delayed clock signal by 1/N (where N is an integer number equal to or larger than 2) to generate an output clock signal.