Ring Oscillator TDC with Dual-Edge Counting for Stable Timing
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Solution Overview
Problem
Time-to-digital converters face challenges in accurately measuring short time intervals due to the asynchronous nature of physical effects, leading to uncertainty in counter values, especially in applications like time-of-flight cameras where average distance to objects is detected as a single number.
Innovation Solution
The implementation of a ring oscillator with multiple inverting elements, where two counters are triggered by different clock edges, and a decoder selects the correct counter value based on the logical states of the inverting elements, eliminating uncertainty by choosing the counter value independent of time differences between edge occurrence and counter update.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single counter is used in a ring oscillator-based TDC, then the device complexity is reduced, but measurement precision deteriorates due to inherent uncertainty in counter values
Solution Approach 1:
The patent divides the counting function into two separate counters: a first counter that counts positive edges and a second counter that counts negative edges. This segmentation allows each counter to capture events during its active phase, eliminating the uncertainty that occurs when a single counter tries to capture both rising and falling edges. The measurement precision is improved because the event occurrence can be unambiguously associated with the active counter's value.
2Measurement precision
If two counters are used to eliminate uncertainty, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent merges the functionality of two counters with a single ring oscillator structure. Both counters share the same ring oscillator clock source and the same physical infrastructure, but operate in complementary phases. This combining approach achieves high measurement precision while minimizing the increase in device complexity, as the two counters are tightly integrated rather than being separate independent units.
Solution Approach 2:
The patent introduces dynamic switching between the two counters based on the phase of the ring oscillator. The first counter is active during one phase and the second counter is active during the opposite phase. This dynamic allocation of counting responsibilities allows the system to maintain high measurement precision while managing complexity through time-multiplexed operation rather than requiring both counters to operate simultaneously and independently.
3Ease of operation
If counter values are updated asynchronously with edge transitions, then the counting process is simplified, but reliability deteriorates due to time difference between edge occurrence and counter update
Solution Approach 1:
The patent implements preliminary action by having counters continuously count during their active phase before an event occurs. When an event is detected, the counter that is currently active has already been counting, so its value immediately reflects the event timing without requiring a subsequent update operation. This eliminates the time difference between edge occurrence and counter value availability, improving reliability while keeping the counting process simple.
Data Source
AI summary
A time-to-digital converter arrangement has a ring oscillator with a plurality of inverting elements and a first and a second counter coupled to the ring oscillator. The first counter is configured to increment a first counter value if a positive edge transition is present at one of the inverting elements. The second counter is configured to increment a second counter value if a negative edge transition is present at the one of the inverting elements. A storage element stores the first and the second counter value and logical states of the plurality of inverting elements. A decoder coupled to the storage element selects one of the first and the second counter value as a valid value based on an evaluation of the stored logical states, and outputs a total counter value based on the valid value and the stored logical states.