Ring Oscillator TDC with Dual-Edge Counting for Precise Timing
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Solution Overview
Problem
Conventional time-to-digital converters face challenges in achieving high accuracy due to the asynchronous nature of physical effects measured, leading to uncertainty in counter values, especially when measuring short time intervals.
Innovation Solution
The implementation of a ring oscillator with multiple inverting elements, where two counters are triggered by different clock edges (positive and negative edges) and a decoder evaluates the logical states to select the correct counter value, eliminating uncertainty by storing and evaluating the logical states and counter values to determine a stable total counter value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single counter is used in conventional TDC design, then the device complexity is reduced, but measurement precision deteriorates due to inherent uncertainty in counter values
Solution Approach 1:
The single counter is segmented into two separate counters (first counter and second counter), each handling different clock edges independently. This segmentation eliminates the uncertainty inherent in a single counter by distributing the counting function across multiple specialized counters, thereby improving measurement precision without significantly increasing overall system complexity.
Solution Approach 2:
A decoder is introduced as an intermediary component that evaluates the logical states of ring oscillator elements and selectively combines the outputs of the two counters. This intermediary resolves the uncertainty by determining which counter value is valid based on the current oscillation state, thereby improving measurement accuracy while maintaining manageable device complexity.
2Measurement precision
If counter update is performed asynchronously with clock edge progression, then the device complexity is reduced, but measurement precision deteriorates due to time difference between edge occurrence and counter update
Solution Approach 1:
The system incorporates feedback by monitoring the logical states of ring oscillator elements and using this information to validate counter values. The decoder continuously evaluates the current oscillation state and uses this feedback to determine which counter output is valid, thereby compensating for timing differences and improving measurement precision without requiring complex synchronization mechanisms.
Solution Approach 2:
The logical states of the ring oscillator elements are captured and stored in advance before the counter values are finalized. This preliminary action allows the decoder to evaluate the correct state corresponding to each clock edge transition, ensuring that the selected counter value accurately reflects the timing event even though the counter update occurs asynchronously.
3Measurement precision
If only one counter is used to measure time intervals, then the device complexity is reduced, but measurement precision deteriorates due to inability to distinguish different edge transitions
Solution Approach 1:
The counting function is segmented into two specialized counters: one dedicated to detecting positive clock edges and another dedicated to detecting negative clock edges. This segmentation allows precise identification and measurement of different edge transitions, improving measurement precision while the modular counter configuration keeps device complexity manageable.
Solution Approach 2:
The two counters are configured asymmetrically with different triggering conditions (one triggered by positive edges, the other by negative edges). This asymmetric configuration allows the system to precisely distinguish between different types of edge transitions, improving measurement accuracy by capturing the specific characteristics of each transition type.
Data Source
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Figure 5~6B
AI summary
A time-to-digital converter arrangement has a ring oscillator (RO) with a plurality of inverting elements (I) and a first and a second counter (CT0, CT1) coupled to the ring oscillator. The first counter is configured to increment a first counter value (C0) if a positive edge transition is present at one of the inverting elements. The second counter is configured to increment a second counter value (C1) if a negative edge transition is present at the one of the inverting elements. A storage element (STO0) stores the first and the second counter value and logical states of the plurality of inverting elements. A decoder (DEC0) coupled to the storage element (STO0) selects one of the first and the second counter value as a valid value based on an evaluation of the stored logical states, and outputs a total counter value based on the valid value and the stored logical states.