Ring Oscillator Circuit for 50% Duty Cycle Wave Shaping

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Solution Overview

Problem

Existing oscillation circuits using ring oscillators struggle to generate a rectangular wave AC signal with a duty cycle of approximately 50% without requiring additional components like frequency dividers, which can increase power consumption and chip size.

Innovation Solution

The oscillation circuit incorporates a current mirror circuit and a voltage buffer to shape the AC signal, ensuring equal source and sink currents through specific transistors, thereby achieving a 50% duty cycle without the need for frequency dividers, and includes a low-pass filter to suppress high-frequency noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a frequency divider is added to achieve a 50% duty cycle, then the duty cycle precision is improved, but the device complexity and power consumption increase

Engineering Contradiction:
Improveduty cycle precisionVSAvoidcircuit complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent combines the duty cycle adjustment function with the existing ring oscillator circuit by integrating specific transistor configurations (first and second transistors with coupled gates and drains) that directly shape the output waveform. This merging eliminates the need for separate frequency dividers while achieving the desired 50% duty cycle, thereby reducing device complexity and power consumption.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces intermediate transistor stages (first transistor coupled to second transistor, third transistor coupled to fourth transistor) that act as mediators to transform the ring oscillator output into a balanced rectangular wave. These intermediary components enable duty cycle control without requiring additional frequency division circuitry, thus improving duty cycle precision while avoiding the complexity of separate divider circuits.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If a frequency divider is added to achieve a 50% duty cycle, then the duty cycle precision is improved, but the chip size increases

Engineering Contradiction:
Improveduty cycle precisionVSAvoidchip size
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent merges the duty cycle control functionality into the core ring oscillator circuit by using coupled transistor pairs (first and second transistors, third and fourth transistors) that directly generate the balanced output waveform. This integration eliminates the need for separate frequency divider circuits, thereby achieving 50% duty cycle precision while minimizing additional chip area consumption.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If additional components are added to shape the AC signal, then the signal quality is improved, but the device complexity increases

Engineering Contradiction:
Improvesignal qualityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines signal shaping functionality with the oscillation generation circuit by integrating specific transistor configurations (first transistor with drain coupled to second transistor gate, third and fourth transistors coupled to fifth transistor) that simultaneously generate and shape the rectangular wave output. This merging achieves high signal quality with 50% duty cycle while avoiding the complexity of separate signal conditioning circuits.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12438529B2Oscillation circuit
Publication Date: 2025.10.07 KK TOSHIBA
  • US12438529B2 patent drawing
  • US12438529B2 patent drawing
  • US12438529B2 patent drawing

AI summary

According to one embodiment, an oscillation circuit includes: a ring oscillator; a first transistor having a gate terminal coupled to an output port of the ring oscillator and a drain terminal coupled to a first node; a second transistor having a drain terminal and a gate terminal that are both coupled to the first node; a third transistor having a gate terminal coupled to the first node and a drain terminal coupled to a second node; a fourth transistor having a gate terminal coupled to the first node and a drain terminal coupled to a third node; a fifth transistor having a drain terminal coupled to the second node and a source terminal coupled to the third node; and a voltage buffer having an input port coupled to the second node.