Ring Oscillator Gate Length Variation Detection in Semiconductor Devices
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Solution Overview
Problem
The challenge is to minimize the impact of gate length variation on circuit characteristics and increase the good product ratio (yield) in semiconductor devices, particularly due to variations in transistor characteristics caused by miniaturization, where existing methods struggle to accurately detect and manage gate length variations across wafer surfaces effectively.
Innovation Solution
A semiconductor device with a ring oscillator configuration that includes multiple transistors of the same and different gate lengths, connected through inverters and switches, allowing for the measurement of oscillating signals and operating currents to calculate gate lengths and apply corrections, thereby minimizing gate length variations and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If gate length measurement is performed in all wafers or in various spots, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent replaces mechanical/optical measurement systems with electrical measurement systems. Instead of using physical measurement tools to directly measure gate length dimensions, the invention uses ring oscillators whose oscillation frequencies are determined by gate length, allowing electrical extraction and measurement of gate length parameters through frequency measurements.
Solution Approach 2:
The patent creates electrical copies or models of gate length characteristics through ring oscillator circuits. The oscillation frequency of the ring oscillator serves as an electrical representation or copy of the gate length parameter, enabling indirect but accurate measurement without direct physical contact or complex optical systems.
2Ease of manufacture
If test device is arranged in scribe, then ease of manufacture is improved, but measurement precision deteriorates due to detection limit
Solution Approach 1:
The patent segments the measurement function by placing multiple ring oscillator test devices at different locations within the scribe region. This segmentation allows coverage of gate length variations across the entire wafer surface by combining measurements from multiple distributed test devices, overcoming the detection limits of single-point measurements.
3Measurement precision
If test device is arranged in chip, then measurement precision is improved, but device complexity increases due to additional measurement pad
Solution Approach 1:
The patent makes the measurement pad universal by designing it to serve multiple functions: it is used for both product sorting tests and for gate length measurements. The same pad structure and test access points are utilized for different measurement purposes, eliminating the need for dedicated separate pads and reducing overall device complexity.
Solution Approach 2:
The patent merges the product testing function with the gate length measurement function into a single integrated system. By combining these functions, the invention eliminates redundant structures and reduces the number of separate test access points required, thereby simplifying the overall device architecture.
4Adaptability or versatility
If ring oscillator configuration is changed to inverter, NAND, NOR or fan-out is changed, then adaptability is improved, but measurement precision deteriorates as gate length variation cannot be directly extracted
Solution Approach 1:
The patent systematically changes the parameters of the ring oscillator (such as the number of inverters, their configurations, and loading conditions) while maintaining the core measurement mechanism. By establishing known relationships between these parameters and oscillation frequency, the invention achieves both adaptability in circuit design and precision in gate length extraction through careful parameter selection and calibration.
Data Source
AI summary
The present disclosure relates to a semiconductor device, an operation method of a semiconductor device, and a manufacturing method of a semiconductor device which are capable of minimizing influence of a gate length variation on a circuit characteristic and increasing a good product ratio (yield) in a product sorting test. A ring oscillator configured such that the plurality of inverters is connected in a ring-like form, and gate capacitors of the transistors are connected to respective output terminals of the plurality of inverters as a load capacitor outputs an oscillating signal, the ring oscillator is configured with a plurality of transistors having the same gate length, and at least two or more ring oscillators including a plurality of transistors having different gate lengths are configured. At the time of product test, the gate length is calculated on the basis of frequencies of oscillating signals of a plurality of ring oscillators, and a back bias is applied in accordance with a correction value corresponding to the calculated gate length, and an operation is performed. The present disclosure can be applied to semiconductor devices.