Ring Oscillator Performance Prediction for IC Binning
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Solution Overview
Problem
Current methods for predicting integrated circuit performance are inaccurate due to manufacturing variations, leading to unreliable decisions on power consumption and performance optimization.
Innovation Solution
The method involves selecting cells on a chip to capture manufacturing variations, building ring oscillators from these cells, and using a linearly fitted model to predict critical path delays, power consumption, and thermal effects, considering variations in transistor and environmental parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If several ring oscillators are placed in different locations on each chip to identify worst case performance, then device complexity increases, but measurement precision remains insufficient for confident performance decisions
Solution Approach 1:
The patent transforms the measurement approach by changing from direct critical path measurement to indirect measurement through ring oscillator frequency parameters. By measuring RO frequencies and using regression analysis to predict critical path performance, the system achieves accurate performance prediction without directly measuring complex critical paths, thus improving measurement precision while controlling device complexity
Solution Approach 2:
Ring oscillators serve as intermediary structures that indirectly represent critical path performance. Instead of directly measuring the complex critical path delays, the patent uses RO frequencies as intermediate parameters that correlate with critical path behavior, enabling accurate performance prediction through a simpler measurement approach
2Reliability
If supply voltage is increased to meet performance requirements, then performance reliability improves, but power consumption increases
Solution Approach 1:
The patent implements feedback by measuring actual ring oscillator frequencies on each chip, using regression analysis to predict critical path performance, and then adjusting supply voltage based on this feedback. This closed-loop approach allows the system to determine the minimum voltage needed to meet performance requirements, ensuring reliability while minimizing power consumption by avoiding excessive voltage headroom
Solution Approach 2:
The system dynamically adjusts supply voltage based on measured performance characteristics rather than using a fixed conservative voltage level. By predicting critical path delay from RO measurements and calculating the minimum required voltage, the system adapts the operating voltage to actual chip performance, optimizing the trade-off between reliability and power consumption
3Measurement precision
If manufacturing variations are not accounted for, then device complexity remains low, but prediction accuracy deteriorates
Solution Approach 1:
The patent performs preliminary characterization during manufacturing by measuring ring oscillator frequencies and constructing regression models that capture manufacturing variations. This preliminary action creates a predictive model specific to each chip's actual performance characteristics, enabling accurate predictions while accounting for process variations without requiring overly complex real-time measurement systems
Solution Approach 2:
The patent replaces direct mechanical/electrical measurement of complex critical path delays with a substituted measurement system using ring oscillators. By measuring RO frequencies and using statistical regression to predict critical path performance, the system substitutes a simpler, more reliable measurement approach that accurately captures manufacturing variations without directly measuring the complex critical path
Data Source
AI summary
This invention places plural ring oscillators on a semiconductor chip during manufacture. The respective oscillation frequencies of these ring oscillators are measured. The semiconductor chip is assigned a grade dependent upon the measured frequencies. The ring oscillators are disposed proximate to critical paths on the semiconductor chip and employ circuit types to model the critical path operation under as many the manufacturing variations as possible. A linearly fitted model of ring oscillator frequencies to critical path delays is constructed during characterization after manufacture.