Power-Supply-Insensitive Ring Oscillator Buffer for Jitter Reduction
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Solution Overview
Problem
Conventional integrated circuits experience jitter in clock networks and phase locked loop (PLL) oscillators due to modulation of the power supply voltage, leading to variations in transition delays and clock output frequency.
Innovation Solution
A power-supply-insensitive delay circuit is created by coupling an inverter sub-circuit with a current-starved inverter sub-circuit, and an auto-tuning circuit is used to calibrate the ring oscillator, adjusting bias current to reduce jitter caused by changes in the power supply voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional inverter circuits are used in clock networks, then the circuit structure is simple, but jitter is generated due to power supply voltage modulation
Solution Approach 1:
The inverter circuit is divided into two separate sub-circuits: a first inverter sub-circuit and a second inverter sub-circuit. Each sub-circuit has opposite delay sensitivity to power supply voltage changes. By segmenting the original inverter into these two functional parts and combining them, the patent achieves cancellation of delay variations while maintaining overall circuit simplicity.
Solution Approach 2:
The patent changes the operating parameters of the two inverter sub-circuits such that they have opposite delay sensitivity characteristics to power supply voltage. The first sub-circuit is designed with negative delay sensitivity while the second has positive delay sensitivity. By adjusting these parameters and combining the sub-circuits in parallel, the overall delay becomes insensitive to power supply variations, reducing jitter.
2Adaptability or versatility
If the power supply voltage varies, then the transition delay changes, but the power supply voltage must be allowed to vary for normal operation
Solution Approach 1:
The patent applies the counterweight principle by designing two inverter sub-circuits with opposite delay sensitivity characteristics. When power supply voltage changes cause delay variation in one sub-circuit, the other sub-circuit produces an equal and opposite delay variation. These counteracting effects cancel each other out, allowing the circuit to tolerate power supply variations while maintaining stable clock frequency.
Solution Approach 2:
The patent implements a feedback mechanism where the delay variations from the two inverter sub-circuits naturally compensate for each other in response to power supply voltage changes. The auto-tuning circuit monitors the overall delay and adjusts the bias current to maintain optimal operating conditions, creating a self-correcting system that adapts to power supply variations.
3Reliability
If auto-tuning circuit is added to calibrate ring oscillator, then jitter is reduced, but circuit complexity increases
Solution Approach 1:
The auto-tuning circuit performs self-calibration of the ring oscillator by monitoring its own operation and automatically adjusting the bias current to optimal values. This self-service capability eliminates the need for external manual calibration and reduces jitter without requiring complex external control systems. The circuit uses its own output frequency information to drive the tuning process.
Solution Approach 2:
The auto-tuning circuit uses feedback from the ring oscillator's output frequency to control the bias current adjustment. The frequency monitor detects variations in the oscillator frequency and feeds this information back to the bias current control, which automatically adjusts the current to maintain optimal oscillation conditions and minimize jitter.
Data Source
AI summary
One embodiment of the present invention sets forth a technique for reducing jitter caused by changes in a power supply for a clock generated by a ring oscillator of inverter devices. An inverter sub-circuit is coupled in parallel with a current-starved inverter sub-circuit to produce an inverter circuit that is insensitive to changes in the power supply voltage. When the ring oscillator is used as the voltage controlled oscillator of a phase locked loop, the delay of the inverters may be controlled by varying a bias current for each inverter in response to changes in the power supply voltage to reduce any jitter in a clock output produced by the changes in the power supply voltage. When the transistor devices are sized appropriately and the bias current is adjusted, the sensitivity of the inverter circuit to changes in the power supply voltage may be reduced.