Ring Oscillator TRNG with Capacitive Jitter Amplification
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Solution Overview
Problem
Ring Oscillator (RO) based True Random Number Generators (TRNGs) face challenges in amplifying jitter noise effectively, leading to high power consumption and limited scalability, especially in portable devices and sensor node applications, due to the requirement for high frequency oscillators and large area overhead.
Innovation Solution
A true random number generator design that includes a first ring oscillator with a high frequency, a second ring oscillator with a lower frequency, and a third ring oscillator with an even lower frequency, capacitively coupled to increase jitter, along with a D-type flip-flop to generate random numbers, allowing for reduced power consumption and increased randomness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the frequency of the fast ring oscillator is increased to amplify jitter noise, then the randomness of the output bits is improved, but the power consumption increases
Solution Approach 1:
A jitter amplification circuit is introduced as an intermediary component between the slow ring oscillator and the fast ring oscillator. This circuit amplifies the jitter noise from the slow oscillator, allowing the fast oscillator to operate at lower frequency while still achieving sufficient randomness in the output bits, thereby reducing power consumption
Solution Approach 2:
The invention changes the frequency parameters of the ring oscillators, specifically operating the fast ring oscillator at a lower frequency (e.g., 10-100 times higher than slow RO, rather than the conventional 1000 times higher). This parameter change reduces power consumption while maintaining randomness through the jitter amplification mechanism
2Measurement precision
If the number of stages or additional analog circuits is increased to amplify jitter, then the jitter of the slow ring oscillator is improved, but the area overhead increases
Solution Approach 1:
A dedicated jitter amplification circuit serves as an intermediary that efficiently amplifies jitter without requiring multiple oscillator stages. This circuit uses a compact design with minimal additional components, achieving effective jitter amplification while maintaining small area overhead
Solution Approach 2:
The invention replaces the mechanical approach of adding more oscillator stages with an electronic jitter amplification circuit. This substitution achieves the same jitter amplification effect with fewer physical components and smaller area
3Measurement precision
If the frequency ratio between fast and slow ring oscillators is increased, then the randomness is improved, but the power consumption increases
Solution Approach 1:
The invention optimizes the frequency ratio parameter between fast and slow ring oscillators, reducing it from the conventional 1000:1 to a lower ratio (10-100:1). This parameter change is made possible by the jitter amplification circuit, which compensates for the reduced frequency difference and maintains randomness while significantly reducing power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves improved randomness with low power consumption and small active area, enabling scalable and high-throughput true random number generation suitable for portable devices and cryptography applications.
Implementation Method 1
a capacitor connected between the second ring oscillator and the third ring oscillator to provide a capacitive coupling therebetween
Data Source
AI summary
Embodiments provide a true random number generator. The true random number generator may include a first ring oscillator having a first frequency, a second ring oscillator having a second frequency, a third ring oscillator having a third frequency, and a capacitor connected between the second ring oscillator and the third ring oscillator to provide a capacitive coupling therebetween. The second frequency is lower than the first frequency, and the third frequency is lower than the second frequency. The true random number generator may further include a D-type flip-flop having a data input connected to an output of the first ring oscillator and having a clock input connected to an output of the third ring oscillator, wherein the D-type flip-flop is configured to generate an output signal representing a sequence of random numbers.