Flip-Flop Ring Oscillator for Individual Logic Cell Delay Measurement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for measuring signal propagation delay in logic cells only provide an average of both rising and falling edge delays, which is insufficient for accurately correlating CAD designs with actual integrated circuit implementations, especially as technology advances and circuit complexity increases.
Innovation Solution
A logic cell delay test and characterization circuit using a flip-flop type ring oscillator with a plurality of logic cells in series, where a switch supplies either rising or falling edge signals, allowing for separate measurement of rising and falling edge delays by varying the oscillation path, enabling precise calculation of delays for individual logic cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a ring oscillator is used to measure logic cell delay, then the measurement can be performed in silicon, but only an average of rise and fall delays is obtained
Solution Approach 1:
The patent segments the oscillation path using switches to create separate measurement paths for rising edge signals and falling edge signals. By controlling the switches, the oscillation can be directed to pass through logic cells in different states (rising or falling), allowing independent measurement of each delay type rather than measuring only their average.
2Device complexity
If traditional ring oscillator methods are used, then the measurement circuit is simple, but separate rising and falling delay measurements cannot be obtained
Solution Approach 1:
The patent introduces dynamic switching control to the ring oscillator circuit. The switches are controlled dynamically to reconfigure the oscillation path during different phases of operation, enabling the same physical circuit to perform multiple measurement functions (rising edge measurement, falling edge measurement) with enhanced precision while maintaining reasonable circuit complexity.
3Reliability
If CAD designs are to be accurately correlated with actual circuits, then separate rise and fall delay data is needed, but traditional methods only provide average delay
Solution Approach 1:
The patent employs feedback mechanisms where the output of the logic cells is fed back to the input through the controlled oscillation path. This feedback loop, combined with the switching control, allows the system to repeatedly measure and accumulate delay data for both rising and falling edges, providing reliable and accurate delay characteristics that can be used to correlate CAD designs with actual circuit behavior.
Data Source
AI summary
A test circuit measures both the rising edge delay and the falling edge delay associated with a logic cell. The test circuit includes a flip-flop type ring oscillator with two groups of logic cells connected in series in the oscillation path. A first multiplexor switches the ring oscillator between a rising edge and a falling edge mode. A second multiplexer causes the second group of logic cells to be included or excluded from the oscillation path. By measuring the oscillation period in the various modes, the rising edge and falling edge delays can be individually calculated.