Ring Oscillator Parasitic Extraction Structure for BEOL Calibration
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Solution Overview
Problem
Conventional ring oscillator circuit design faces errors due to inaccurate device models and improper back-end-of-line (BEOL) interconnect parasitic extraction, leading to inaccurate simulation results and subsequent circuit design flaws.
Innovation Solution
A structure for extracting interconnect parasitic in a ring oscillator is introduced, incorporating parasitic resistance and capacitance sub-structures connected to logical units to determine and calibrate errors in polysilicon and metal interconnect parasitic extraction, allowing for precise simulation results and accurate device and BEOL models.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional simulation structure is used without parasitic extraction sub-structures, then device model accuracy is maintained, but simulation results deviate from actual measurement results due to unaccounted BEOL interconnect parasitic errors
Solution Approach 1:
The patent segments the simulation structure by introducing separate parasitic resistance sub-structures and parasitic capacitance sub-structures that are distinct from the logical units. These sub-structures are connected to the logical units through interconnect structures, allowing independent extraction and calibration of parasitic parameters without modifying the core logical unit designs.
Solution Approach 2:
The patent introduces interconnect structures as intermediary elements between the logical units and parasitic sub-structures. These interconnect structures serve as mediators that carry both signal transmission and parasitic parameter extraction functions, enabling the separation of functional simulation and parasitic characterization while maintaining structural integration.
2Measurement precision
If parasitic extraction errors are compensated by adjusting device model capacitance values, then simulation results can be aligned with measurements, but the actual cause of errors cannot be determined and both device model and BEOL model become inaccurate
Solution Approach 1:
The patent separates the parasitic extraction into distinct resistance sub-structures and capacitance sub-structures, each connected through specific interconnect structures. This segmentation allows independent extraction and calibration of parasitic parameters, enabling identification of whether errors originate from device models or BEOL interconnect models without conflating the two through capacitance adjustments.
Solution Approach 2:
The patent implements a calibration mechanism where parasitic parameters are extracted from the dedicated sub-structures and fed back to refine both device models and BEOL models. This feedback loop enables continuous improvement of model accuracy by comparing extraction results with actual measurements and adjusting parameters accordingly, rather than using one-time compensatory adjustments.
3Measurement precision
If BEOL interconnect parasitic extraction is performed without dedicated sub-structures, then simulation structure remains simple, but extraction accuracy is insufficient leading to design errors
Solution Approach 1:
The patent divides the parasitic extraction system into dedicated resistance sub-structures and capacitance sub-structures, each with specific geometric configurations (serpentine for resistance, comb/interdigitated for capacitance). This segmentation enables accurate extraction of different parasitic components through their respective sub-structures without requiring complex integrated extraction methodologies.
Solution Approach 2:
The parasitic sub-structures serve multiple functions: they act as test structures for parasitic parameter extraction, provide calibration data for model refinement, and maintain structural compatibility with standard fabrication processes. The interconnect structures similarly serve both signal transmission and parasitic coupling functions, reducing the need for separate dedicated test structures.
Data Source
AI summary
A structure for extracting interconnect parasitic in a ring oscillator is disclosed. The ring oscillator comprises multiple logical units connected in head to tail series. The structure comprises parasitic resistance sub-structures and/or parasitic capacitance sub-structures each connected to a corresponding logical unit. The structure can be used to determine errors in extracting parasitic resistance of polysilicon interconnects and metal interconnects, and/or errors in extracting parasitic capacitance between the polysilicon interconnects and between the metal interconnects. Therefore, the parasitic extraction error can be calibrated accordingly to obtain more precise circuit simulation results and more accurate device model and BEOL model.