Ring Oscillator Resonance Topology for Low-Voltage Phase Noise
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Solution Overview
Problem
In CMOS technologies, reducing phase noise in oscillators while maintaining power efficiency is challenging, especially at low supply voltages, as increasing supply voltage is less attractive for reliability reasons, and quadrature VCOs require high parasitic capacitance and complementary transistors for efficient operation.
Innovation Solution
The oscillator circuit design includes N amplifier circuits connected in a ring with first and second resonance circuits, using NMOS transistors and a second resonance circuit with a higher resonance frequency to reduce parasitic capacitance and supply voltage requirements, allowing for efficient operation at low supply voltages and improved phase noise performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the supply voltage is increased to reduce phase noise, then the phase noise performance is improved, but the reliability deteriorates due to state-of-the-art CMOS technology constraints
Solution Approach 1:
The patent changes the circuit topology from conventional parallel resonance tanks to series resonant cells, which fundamentally alters the voltage-stress distribution. This topological parameter change allows the oscillator to achieve better phase noise performance at lower supply voltages, thereby improving reliability without sacrificing phase noise performance. The series resonance configuration naturally provides better voltage stress distribution across the resonant elements.
2Use of energy by moving object
If quadrature VCOs use complementary devices to increase effective transconductance, then power efficiency is improved, but device complexity increases due to requiring complementary transistors
Solution Approach 1:
The patent extracts and removes the complementary transistor requirement from the quadrature VCO design. By using a different approach based on series resonant cells with simple NMOS transistors, the invention achieves comparable or better power efficiency without the complexity of complementary device pairs. This extraction of the complementary transistor requirement simplifies the device structure while maintaining power efficiency.
Solution Approach 2:
The patent uses four identical series resonant cell copies connected in a ring configuration to generate quadrature signals. Instead of using complex complementary transistors, the invention replicates a simple series resonant cell four times with appropriate phase shifting, achieving quadrature functionality through structural repetition rather than device complexity.
3Device complexity
If series resonant cells are used to generate quadrature signals, then device complexity is reduced, but phase noise performance deteriorates at low supply voltages
Solution Approach 1:
The patent optimizes key parameters of the series resonant cells including L/C ratio, quality factor Q, and transconductance gM to achieve superior phase noise performance. By carefully adjusting these parameters, the invention overcomes the traditional limitation of series resonant cells at low supply voltages. The optimized parameters enable the simple series resonant structure to deliver both low complexity and excellent phase noise performance.
Solution Approach 2:
The patent introduces dynamic biasing and control mechanisms to the series resonant cells, allowing the transconductance and resonant frequency to be dynamically adjusted. This dynamic control enables the circuit to maintain optimal performance across varying supply voltages, particularly improving phase noise at low supply voltages while keeping the device structure relatively simple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves high power efficiency and reduced phase noise with supply voltages slightly higher than the threshold voltage, enabling robust quadrature oscillation and improved DC to RF conversion efficiency, while minimizing parasitic capacitance and phase noise.
Implementation Method 1
each of the N amplifier circuits comprises a first resonance circuit comprising a first inductor and a first capacitor, wherein the first inductor is connected between the internal node and the output of the amplifier circuit, and the first capacitor is connected between the output of the amplifier circuit and one of the first and the second supply terminals. Moreover, each of the N amplifier circuits comprises a second resonance circuit comprising a second inductor and a second capacitor
Data Source
AI summary
An oscillator circuit (15) is disclosed. It comprises N amplifier circuits (A1-A4), connected in a ring and has a first and a second supply terminal (s1, s2). Each amplifier circuit (A1-A4) comprises an input transistor (M1) having its gate connected to the input (in) of the amplifier circuit, its drain connected to an internal node (x) of the amplifier circuit, and its source connected to the first supply terminal (si). Furthermore, each amplifier circuit (A1-A4) comprises a first resonance circuit (R1) comprising a first inductor (Ls) and a first capacitor (Cs), wherein the first inductor (Ls) is connected between the internal node (x) and the output (out) of the amplifier circuit, and the first capacitor (Cs) is connected between the output (out) of the amplifier circuit and one of the first and the second supply terminals (s1, s2). Moreover, each amplifier circuit (A1-A4) comprises a second resonance circuit (R2) comprising a second inductor (Lp) and a second capacitor (Cp), wherein the second inductor (Lp) and the second capacitor (Cp) are connected in parallel between the internal node (x) and the second supply terminal (s2).