Multi-Phase Ring Oscillator Reassembly for Low Jitter Clocks
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Solution Overview
Problem
Conventional ring oscillators in high-speed SERDES systems face challenges with high jitter and power consumption due to phase noise, particularly from flicker noise, which is exacerbated by the reduction in transistor size in advanced processes, and are limited by the number of stages and oscillation frequency.
Innovation Solution
The proposed solution involves a ring oscillator with an increased number of stages and a phase selector circuit that reassembles multi-phase signals, allowing only N phase signals to be used out of M, thereby reducing flicker noise and power consumption while maintaining the same total delay, decoupling oscillation frequency from the number of stages, and using a phase selector circuit to reconstruct the necessary phase clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of stages in a ring oscillator is increased to reduce phase noise, then phase noise performance improves, but power consumption increases proportionally
Solution Approach 1:
The invention segments the M phase signals generated by the ring oscillator into N groups, where each group contains M/N signals. A phase selector circuit then selects one signal from each group to form the N output phase signals. This segmentation allows the system to use fewer than M stages while achieving the desired phase noise performance, because the phase noise reduction benefit is obtained from having M delay elements without requiring all M signals to be actively used, thus reducing power consumption proportionally to the number of phases actually needed.
2Quantity of substance
If transistor size is reduced in advanced processes to increase integration, then device density improves, but flicker noise increases significantly
Solution Approach 1:
The invention extracts only the necessary N phase signals from the M total phase signals generated by the ring oscillator. By using a phase selector circuit to choose only M/N signals from each of N groups, the system obtains the required clock phases without utilizing all M signals. This extraction approach allows the ring oscillator to have M stages for adequate phase noise performance while actually using fewer signals, thereby reducing the total flicker noise contribution from the transistor devices without sacrificing device density benefits from advanced processes.
3Area of stationary object
If conventional ring oscillators are used for clock generation, then area is minimized and multiple phases are provided, but jitter and phase noise performance deteriorate
Solution Approach 1:
The invention introduces a dynamic phase selector circuit that can selectively choose from M different phase signals to generate N output phases. This dynamic selection mechanism allows the system to adaptively optimize phase noise performance by utilizing all M ring oscillator stages for frequency division and phase generation, while the selector circuit dynamically picks the best combination. This maintains the compact area advantage of ring oscillators while dramatically improving jitter and phase noise through intelligent signal reassembly from multiple phases.
Data Source
AI summary
Technologies for low jitter and low power ring oscillators with multi-phase signal reassembly are described. A ring oscillator circuit includes a ring oscillator with a set of M delay stages, each stage outputs a phase signal, where M is a positive integer greater than one. The ring oscillator circuit includes a phase selector circuit coupled to the ring oscillator. The phase selector circuit can receive M phase signals from the ring oscillator and generate N phase signals based on the M phase signals, where N is a positive integer less than M.