Injection-Locked Ring Oscillator Clock Receiver With Phase Delay Tuning
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Solution Overview
Problem
Existing clock receivers face difficulties in accurately adjusting the oscillation frequency of ring oscillators due to process variations, making it challenging to synchronize with low power clock signals without increasing power consumption.
Innovation Solution
A clock receiver design that includes a ring oscillator with a control circuit capable of adjusting its oscillation frequency using phase signals generated from a reference clock signal, utilizing a sequence of inverters and an early-late detector to control phase delays, allowing for precise frequency alignment with minimal power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the power of the transmitted clock signal is increased to bring the oscillation frequency of the ring oscillator to the desired frequency, then the frequency synchronization accuracy is improved, but the power consumption increases
Solution Approach 1:
The patent implements a control circuit that dynamically adjusts the oscillation frequency of the ring oscillator by modifying the delay of individual inverter stages based on detected phase differences. This dynamic adjustment allows the system to achieve frequency synchronization without requiring high power clock signals, as the frequency is adaptively tuned through controlled delay modification rather than brute-force power injection.
Solution Approach 2:
The patent employs an early-late detector that provides feedback on the phase difference between the reference clock signal and the ring oscillator output. This feedback mechanism enables the control circuit to continuously adjust the inverter delays to minimize phase difference, achieving accurate frequency synchronization with low power consumption by iteratively optimizing the oscillation frequency based on real-time phase error detection.
2Reliability
If the injection power is increased to overcome process variations, then the frequency locking reliability is improved, but the power consumption increases
Solution Approach 1:
The patent changes the delay parameter of individual inverter stages in the ring oscillator to compensate for process variations. By adjusting the delay of specific inverter stages, the control circuit can tune the overall oscillation frequency to match the reference clock frequency, achieving reliable frequency locking without increasing power consumption. This parameter adjustment approach is more efficient than increasing injection power.
Solution Approach 2:
The early-late detector provides continuous feedback on phase alignment, enabling the control circuit to reliably lock the ring oscillator frequency to the reference clock frequency. This feedback-driven adjustment ensures frequency locking reliability under process variations while maintaining low power consumption, as the system adaptively finds the correct frequency match rather than relying on high-power injection.
3Device complexity
If a simple injection-locked solution is used, then the device complexity is reduced, but the frequency adjustment precision deteriorates
Solution Approach 1:
The patent segments the ring oscillator into individual inverter stages, each with independently controllable delay. This segmentation allows the control circuit to precisely adjust the oscillation frequency by modifying the delay of specific stages, achieving high frequency adjustment precision. The segmented approach maintains relatively simple circuitry compared to complex frequency synthesis methods, as it leverages the existing inverter structure with added control capability.
Solution Approach 2:
The control circuit acts as an intermediary between the reference clock signal and the ring oscillator. It receives the reference clock, detects phase differences through the early-late detector, and generates control signals that adjust the inverter delays. This intermediary mechanism enables precise frequency adjustment without requiring complex frequency synthesis circuits, maintaining simplicity while achieving high precision through phased-array delay control.
Data Source
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AI summary
The invention concerns a clock receiver including: a ring oscillator (402) adapted to generate a clock signal, the ring oscillator having a sequence of N inverters, an input of a first inverter (404) being coupled to a feedback node, an input of a second inverter (406) being connected to an output of the first inverter and to an input line (403) for receiving a reference clock signal (IN), and an output of the second inverter (406) or of a third inverter (410) providing a first phase signal (φ1); a further sequence (413) of inverters, an input of a first further inverter (414) being coupled to the feedback node (402), and an output of another further inverter (420) providing a second phase signal (φ2); and a control circuit (424) for adjusting an oscillation frequency of the ring oscillator based on the relative phases of the first and second phase signals.