Ring Oscillator Clock Generation With PLL Current Compensation
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Solution Overview
Problem
Existing electronic clock generation circuits, particularly RC oscillators, are power-intensive and inefficient when generating multiple clock signals at different frequencies, making them unsuitable for low-power applications.
Innovation Solution
A device comprising ring oscillators, phase-locked loops, and current mirrors that generate multiple clock signals with controlled frequency accuracy by using a phase-locked loop to adjust the current supply to each oscillator, reducing power consumption and eliminating the need for multiple capacitive elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If RC oscillators are used to generate multiple clock signals at different frequencies, then each clock signal can be generated independently, but the power consumption increases significantly due to repeated charging of multiple capacitive elements
Solution Approach 1:
The patent merges multiple RC oscillators into a single ring oscillator structure that can generate multiple clock signals simultaneously. Instead of using separate capacitive elements for each frequency, the invention uses a single shared capacitive element that is charged once and then distributed to multiple output frequencies through the ring oscillator topology, thereby eliminating the need to repeatedly charge multiple capacitors and significantly reducing power consumption.
Solution Approach 2:
The single capacitive element in the ring oscillator serves multiple functions by being shared across all clock signal generation paths. This universal capacitive element enables the generation of multiple different frequencies without requiring dedicated capacitive storage for each frequency, allowing one component to perform the work of multiple components in traditional RC oscillator designs.
2Device complexity
If RC oscillators are used for clock signal generation, then the circuit structure is simple, but the frequency accuracy is limited due to the inherent characteristics of RC time constants
Solution Approach 1:
The patent introduces a phase-locked loop (PLL) feedback mechanism that monitors the output frequency of the ring oscillator and adjusts the charging current to the shared capacitive element accordingly. This feedback control system continuously corrects frequency deviations, maintaining high frequency accuracy while preserving the relatively simple ring oscillator structure. The PLL compares the oscillator output with a reference frequency and dynamically adjusts parameters to eliminate frequency errors.
3Adaptability or versatility
If multiple capacitive elements are used in RC oscillators to generate different frequencies, then each frequency can be independently controlled, but the device complexity and power consumption increase
Solution Approach 1:
The patent combines multiple frequency control functions into a single ring oscillator with one shared capacitive element. Instead of having separate capacitors for each frequency output, the invention uses the same capacitive element charged by a controllable current source, allowing different frequencies to be generated by varying the charging current rather than using multiple physical capacitors, thereby reducing device complexity.
Solution Approach 2:
The invention changes the control parameter from capacitive value selection to current magnitude adjustment. By varying the charging current supplied to the single shared capacitive element, different frequencies can be achieved without changing the physical capacitor. This parameter change approach allows flexible frequency control while minimizing the number of discrete components required.
Data Source
AI summary
A device for generating first clock signals includes first circuits, each including a ring oscillator delivering one of the first clock signals and being connected to a first node configured to receive a first current. A circuit selects one the first clock signals, and a phase-locked loop delivers a second signal which is a function of a difference between a frequency of the first selected clock signal and a set point frequency. Each first circuit supplies the first node with a compensation current determined by the second signal, when this first circuit delivers the selected clock signal and operates in controlled mode.