Ring Oscillator PLL with Auxiliary Loop for Phase Noise Suppression

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Solution Overview

Problem

Designing a satisfactory phase-locked loop (PLL) for electronic devices with wireless communications circuitry is challenging due to the difficulty in reducing phase noise associated with ring oscillators, which affects the performance of wireless communications.

Innovation Solution

The implementation of a phase-locked loop circuitry that includes a ring oscillator and an auxiliary digital loop with a second frequency divider having a lower division ratio than the main frequency divider, along with a time-to-digital converter, amplifier, and bandpass filter, to correct phase noise faster than the main PLL cycle time, improving phase noise performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Extent of automation

If a ring oscillator is used in the phase-locked loop, then the PLL can be implemented with digital circuitry, but phase noise performance deteriorates

Engineering Contradiction:
Improvedigital implementationVSAvoidphase noise performance
Core Design Contradiction:
Extent of automationVSReliability

Solution Approach 1:

The PLL is divided into two separate loops: a main PLL for basic frequency synthesis and an auxiliary PLL specifically dedicated to phase noise suppression. The auxiliary loop segments the phase noise correction function from the main locking function, allowing optimized performance in each domain.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A second time-to-digital converter is introduced as an intermediary component in the auxiliary loop to measure phase deviations and generate correction signals. This intermediary mechanism enables digital correction of phase noise without disrupting the main PLL's digital operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If a single frequency divider is used in the main PLL, then the loop is simple, but phase noise correction speed is insufficient

Engineering Contradiction:
Improveloop structureVSAvoidphase noise correction speed
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The frequency division function is segmented into two separate dividers: a first frequency divider in the main loop and a second frequency divider in the auxiliary loop. This segmentation allows the auxiliary loop to operate with a different division ratio optimized for faster phase noise correction.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically adjusts by using two different division ratios simultaneously - the main PLL uses a higher division ratio for stable locking, while the auxiliary PLL uses a lower division ratio for rapid phase noise response, creating adaptive performance across different operating conditions.

Inventive Principle:
Principle #15Dynamics

3Reliability

If an auxiliary digital loop is added to reduce phase noise, then phase noise performance improves, but device complexity increases

Engineering Contradiction:
Improvephase noise performanceVSAvoidloop structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The auxiliary loop components (second TDC, second frequency divider, and filter) are merged into a compact integrated structure that shares the ring oscillator and control logic with the main PLL. This merging reduces the overall complexity increase while maintaining phase noise suppression functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The auxiliary loop implements a feedback mechanism where phase deviations detected by the second TDC are corrected in real-time through the filter and applied to the ring oscillator. This feedback approach systematically reduces phase noise without requiring complex open-loop compensation circuits.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20240072813A1Ring Oscillator Phase-locked Loop with Digital Phase Noise Suppression
Publication Date: 2024.02.29 APPLE INC
  • US20240072813A1 patent drawing
  • US20240072813A1 patent drawing
  • US20240072813A1 patent drawing

AI summary

An electronic device may include wireless circuitry having mixer circuitry configured to receive an oscillator signal from phase-locked loop circuitry. The phase-locked loop circuitry may include a digital or analog phase-locked loop having a first frequency divider, a ring oscillator, and an auxiliary phase noise cancellation loop coupled to the ring oscillator. The auxiliary phase noise cancellation loop may include at least a time-to-digital converter, a second frequency divider, an amplifier, and a bandpass filter configured to reject thermal and quantization noise associated with the time-to-digital converter. The first frequency divider may have a first division ratio, whereas the second frequency divider may have a second division ratio that is less than the first division ratio to provide faster phase noise correction.