Differential Ring Oscillator Tuning for Low-Noise Wide-Range PLLs
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Solution Overview
Problem
High-frequency integrated circuits face challenges in minimizing phase noise and achieving a large tunable frequency range due to noise from supply and substrate sources, which limits the loop bandwidth and output swing of phase locked loops (PLLs).
Innovation Solution
A ring oscillator with variable resistive and capacitive loads, and a variable current source, adjusted by a configuration signal derived from the phase comparator, allows for flexible adjustment of the oscillation frequency and bandwidth without additional biasing stages, reducing phase noise and increasing output swing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the loop bandwidth is increased to minimize jitter, then the tracking speed improves, but the phase noise increases due to additional biasing circuits
Solution Approach 1:
The patent extracts and removes the additional biasing circuits from the PLL architecture. Instead of using self-biased delay cells that require extra biasing circuits (which generate noise), the invention uses a charge pump that directly provides bias currents to the delay elements, eliminating the noisy biasing stages while maintaining fast tracking capability
Solution Approach 2:
The charge pump serves multiple functions simultaneously: it generates the bias currents for the delay elements and provides the control voltage to the VCO. This multi-functionality eliminates the need for separate biasing circuits, reducing noise sources while maintaining the ability to achieve high tracking speeds through wide bandwidth operation
2Object-generated harmful factors
If the output swing is increased to improve signal quality, then the phase noise decreases, but the frequency tuning range is limited by gate voltage
Solution Approach 1:
The patent changes the control parameter from gate voltage to current-based control. By using current-mode operation with programmable current sources, the delay elements can be tuned over a wide frequency range while maintaining large output swings. The current control mechanism allows independent optimization of both output swing amplitude and frequency tuning range without the limitations of voltage-based gate control
3Speed
If additional biasing circuits are added to adjust PLL bandwidth, then the tracking speed improves, but the number of noise sources increases
Solution Approach 1:
The patent merges the bias current generation function into the charge pump circuit itself. The charge pump directly generates and supplies bias currents to the delay elements without requiring separate biasing circuits. This consolidation eliminates additional noise sources while maintaining the capability for fast PLL locking and tracking
Data Source
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AI summary
The present invention relates to a ring oscillator including a plurality of cascaded inverting delay stages, each delay stage includes a differential pair of input transistors, a variable resistive load coupled to each transistor, a differential output between the variable resistive load and the corresponding input transistor, a variable current source coupled to the differential pair of transistors for variably setting a bias current through the differential pair of transistors, and an input coupled to the variable resistive load and the variable current source for receiving an configuration signal, wherein the variable resistive load and the variable current source are changed in response to the configuration signal, such that the bias current increases, while the variable resistive load decreases and vice versa.