Ring Oscillator Timestamp Generator for Low-Frequency Precision Timing

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Solution Overview

Problem

Existing timing generators for electronic circuits, particularly in the automotive sector, face challenges with high precision, stability, and scalability for high-resolution systems, as they are often expensive, prone to malfunction, and unsuitable for low clock frequencies and multiple channels, which limits their use in autonomous driving applications.

Innovation Solution

A timing generator using a ring oscillator with an odd number of delay elements, clock dividers, and a clock generator to produce timestamps with coarse and fine codes, incorporating redundant information to ensure phase correction and robustness, suitable for low clock frequencies and multichannel systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If synchronous electronic circuits operating at high clock frequencies are used to provide precise timecode, then measurement precision is improved, but device complexity increases and reliability deteriorates

Engineering Contradiction:
Improvetime measurement precisionVSAvoidcircuit stability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent changes the operating parameters by using low clock frequencies (less than 300 MHz) instead of high clock frequencies, while achieving high time measurement precision through a different mechanism (Vernier timing generator with delay elements and time-to-digital converter) that does not rely on high-speed synchronous circuit operation

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the mechanical/synchronous clocking system with an asynchronous timing generation approach using Vernier delay elements and time-to-digital conversion, eliminating the need for high-frequency synchronous circuit operation while maintaining or improving time measurement precision

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If classical Vernier schema timing generators are used to achieve high resolution time-to-digital conversion, then measurement precision is improved, but device complexity and power consumption increase due to scaling requirements for multiple channels

Engineering Contradiction:
Improvetime-to-digital conversion resolutionVSAvoidnumber of timing generators required
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges multiple timing functions into a single timing generator unit that can serve multiple channels through time-multiplexed operation, eliminating the need for separate timing generators for each channel while maintaining high resolution time-to-digital conversion capability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent employs periodic time-multiplexed operation where a single timing generator sequentially serves multiple channels in time-divided fashion, allowing one generator to handle multiple channels that would otherwise require multiple simultaneous generators, thus reducing overall device complexity

Inventive Principle:
Principle #19Periodic action

3Measurement precision

If multiple timing generators are used to achieve high-resolution systems with many parallel channels, then measurement precision is improved, but use of energy increases

Engineering Contradiction:
Improvetime measurement resolutionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent combines multiple channel timing functions into a single power-efficient timing generator that time-multiplexes across channels, eliminating the need for multiple parallel generators and thus significantly reducing total power consumption while maintaining high measurement precision for all channels

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20230400877A1Timing generator as master clock for an electronic circuit
Publication Date: 2023.12.14 ELMOS SEMICON AG
  • US20230400877A1 patent drawing
  • US20230400877A1 patent drawing
  • US20230400877A1 patent drawing

AI summary

A timing generator as master clock for an electronic circuit includes a coarse code and a plurality of fine codes, has a ring oscillator with an uneven number n of delay elements, each of which has a delay output at which clock signal is present; clock dividers which are connected to the delay outputs and at whose output a clock divider output signal is output; start circuit for generating initialization signal to trigger clock dividers, and clock generator that further processes clock signal and generates a coarse code, and an output at which generated timestamp is output, wherein the fine codes of timestamp are formed from clock divider output signals of the clock dividers, and the coarse code and the fine codes contain redundant information that a time shift of the fine codes relative to the coarse code by at most (n−1)/2 time differences results in a correct timestamp.