Ring Oscillator DCO with Sigma-Delta Fine Frequency Control

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Solution Overview

Problem

High-resolution digital phase-locked loops (DPLLs) require a large number of bits in the digitally-controlled oscillator (DCO) code, leading to increased area and power consumption, and are affected by process, voltage, and temperature (PVT) variations, resulting in degraded resolution and unwanted jitter.

Innovation Solution

Incorporating a sigma-delta modulator (SDM) into the DCO circuit, which modulates the least significant bits at a higher frequency than the time-to-digital converter (TDC), averaging frequency deltas and providing fine-tuning to reach a steady state frequency, combined with a digital-to-analog converter (DAC) to generate currents for a ring oscillator, enhancing resolution with reduced power and area requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a large number of bits are used in the DCO code to achieve high resolution, then the frequency control resolution is improved, but the area and power consumption of the DPLL components increase

Engineering Contradiction:

Improvefrequency control resolutionVSAvoidDPLL component area

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent segments the frequency control into two parts: a coarse frequency control using a smaller number of bits in the DCO code, and a fine frequency control using the SDM to generate additional bits. This segmentation allows achieving high overall resolution without requiring a large number of bits in the original DCO code, thereby reducing the area and power consumption of the DCO while maintaining high frequency control resolution.

Inventive Principle:

Principle #1Segmentation

2Measurement precision

If a large number of bits are used in the DCO code to achieve high resolution, then the frequency control resolution is improved, but the power consumption of the DPLL components increases

Engineering Contradiction:

Improvefrequency control resolutionVSAvoidDPLL power consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

3Adaptability or versatility

If process, voltage, and temperature variations are present, then the DPLL operates in varying conditions, but the effective and worst case actual resolution is degraded

Engineering Contradiction:

ImprovePVT condition adaptabilityVSAvoideffective resolution

Core Design Contradiction:

Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent employs a feedback mechanism where the SDM continuously monitors the phase error between the reference clock and feedback clock, and dynamically adjusts the DCO frequency accordingly. This feedback loop compensates for PVT variations by detecting frequency deviations and correcting them in real-time, thereby maintaining high effective resolution despite process, voltage, and temperature variations.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent implements dynamic frequency adjustment through the SDM, which continuously adapts the DCO frequency based on real-time phase error measurements. This dynamic control mechanism allows the system to respond to PVT variations and maintain optimal performance across varying operating conditions, preventing resolution degradation that would occur with static frequency control.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20230308112A1Sigma-delta modulator for high-resolution control of ring oscillator in digital phase-locked loop

Publication Date: 2023.09.28 INFINEON TECHNOLOGIES AMERICAS CORP

AI summary

A digitally-controlled oscillator (DCO) circuit includes a digital-to-analog converter (DAC) to generate a first current based on most significant bits of a multi-bit code received from a time-to-digital converter (TDC) of a digital phase-locked loop (PLL). The DCO circuit further includes a sigma-delta modulator (SDM) to modulate least significant bits of the multi-bit code into a set of digital bits based on a first frequency of a feedback clock of the DPLL. The set of digital bits is to cause the DAC to generate a second current. The DCO circuit further includes a ring oscillator coupled to the DAC, the ring oscillator to generate an alternating-current (AC) output signal having a second frequency corresponding to a combination of the first current and the second current.