Selectable-Delay Ring Oscillator for Accurate Low-Power Clocks
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Solution Overview
Problem
Ring oscillator circuits used in clock signal generation face a trade-off between low power consumption and frequency accuracy, with reduced delay element size improving frequency accuracy but increasing manufacturing cost and requiring miniaturization technology.
Innovation Solution
A ring oscillator circuit design incorporating multiple first delay circuits and a second delay circuit with varying delay elements connected in a ring-like manner, allowing for adjustable oscillation frequency by selecting different second delay elements, which can be manufactured without advanced miniaturization technology, thus reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delay element size is reduced to improve frequency accuracy, then frequency accuracy is improved, but manufacturing cost increases and miniaturization technology is required
Solution Approach 1:
The patent applies local quality by making delay elements have different delay amounts rather than being uniform. Specifically, the delay elements are designed with delay amounts of 1 unit, 2 units, 4 units, and 8 units respectively, allowing selective combination to achieve precise delay control without requiring all elements to be miniaturized. This resolves the contradiction by achieving frequency accuracy through selective assembly of differently-sized elements rather than universal miniaturization.
Solution Approach 2:
The patent segments the delay function into multiple discrete delay elements with different delay amounts (1, 2, 4, 8 units). By dividing the overall delay requirement into these segmented components, the system can achieve fine-grained frequency control by selecting and combining specific segments, avoiding the need to reduce all elements to minimal size and thus reducing manufacturing costs.
2Measurement precision
If delay element size is reduced to improve frequency accuracy, then frequency accuracy is improved, but manufacturing technology requirements increase
Solution Approach 1:
The patent uses local quality by assigning different delay characteristics to different elements rather than requiring all elements to use advanced miniaturization technology. The delay elements with 1, 2, 4, and 8 unit delays can be manufactured using standard technology, and their selective combination provides the precision that would otherwise require complex miniaturization.
Solution Approach 2:
The patent introduces dynamics by making the delay configuration selectable rather than fixed. The ability to choose different delay elements (1, 2, 4, or 8 units) allows the system to adapt to different frequency requirements, achieving high precision without permanently committing to complex miniaturized structures.
3Measurement precision
If TCXO is used to improve frequency accuracy, then frequency accuracy is improved, but power consumption increases
Solution Approach 1:
The patent segments the delay function into multiple selectable elements with different delay amounts. This segmentation allows the ring oscillator to achieve frequency accuracy comparable to TCXO by selectively combining delay elements, while maintaining the low power consumption advantage of ring oscillators since no temperature compensation circuitry is needed.
Solution Approach 2:
The patent changes the delay parameter by providing elements with different delay amounts (1, 2, 4, 8 units) rather than using uniform delay elements. This parameter variation allows precise frequency control through selection, achieving TCXO-level accuracy while maintaining ring oscillator power efficiency.
Data Source
AI summary
A ring oscillator circuit includes a plurality of first delay circuits each including X first delay elements, and a second delay circuit including a plurality of second delay elements different in delay amount from each other arranged in parallel to each other so as to be alternatively loaded, the plurality of first delay circuits and the second delay circuit are configured to be connected to each other in a ring-like manner, and X is an integer fulfilling X≥1.


