Adjustable Ring Oscillator Clocking for Low-Power Sleep Timing
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Solution Overview
Problem
Integrated circuits, especially battery-powered ones, face challenges in achieving accurate tick times during sleep mode due to the limitations of existing sleep clock signals, which may not provide sufficient accuracy.
Innovation Solution
A device and method that utilize an adjustable ring oscillator to generate a high frequency clock signal with a short cycle, allowing for a trade-off between power consumption and timing accuracy, by adjusting the delay of the ring oscillator to ensure the output cycle matches integer multiples of the sleep cycle and short cycle, thereby enhancing timing precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a sleep clock signal with frequency of 32.768 Khz is used during sleep mode, then power consumption is reduced, but timing accuracy of tick clock deteriorates
Solution Approach 1:
The patent employs a dual-clock system where the clock source dynamically switches between sleep clock (32.768 Khz) and high-frequency clock (e.g., 19.2 Mhz) based on operational requirements. The system uses a counter to accumulate sleep clock cycles and compares against a reference value, triggering high-frequency clock activation when accuracy threshold is approached, thereby dynamically adapting clock frequency to maintain timing accuracy while minimizing power consumption during extended sleep periods.
Solution Approach 2:
The system changes the operating parameters of the clock system by switching between different frequency states. The sleep clock operates at 32.768 Khz for low power, while the high-frequency clock operates at much higher frequencies (e.g., 19.2 Mhz) when timing accuracy requirements demand. This parameter switching is controlled by monitoring the accumulated time deviation and activating the appropriate clock source accordingly.
2Measurement precision
If high frequency clock is continuously active, then timing accuracy is improved, but power consumption increases
Solution Approach 1:
Instead of continuous high-frequency clock operation, the system implements periodic activation of the high-frequency clock. The sleep clock runs continuously at low power, and the high-frequency clock is activated periodically only when the counter indicates that timing accuracy is approaching its threshold. This periodic action maintains timing accuracy while dramatically reducing average power consumption compared to continuous high-frequency operation.
Solution Approach 2:
The system uses the sleep clock itself to monitor and trigger the activation of the high-frequency clock. The counter accumulates sleep clock cycles and automatically triggers high-frequency clock activation when the accumulated value approaches the reference value, creating a self-regulating mechanism that maintains timing accuracy without requiring external intervention or continuous high-power operation.
3Measurement precision
If sleep clock frequency is increased, then timing accuracy is improved, but power consumption increases
Solution Approach 1:
Rather than using a single high-frequency sleep clock, the system dynamically switches between a low-frequency sleep clock (32.768 Khz) and a high-frequency clock (e.g., 19.2 Mhz). The dynamics of the system allow it to operate in low-power mode most of the time, activating high-frequency operation only temporarily when timing accuracy correction is needed, thus achieving accurate timing without the continuous power cost of a high-frequency sleep clock.
Data Source
AI summary
A device and a method for generating a output clock signal having a output cycle, the method includes: (i) adjusting a delay of an adjustable ring oscillator to provide a high frequency clock signal having a short cycle so that the output cycle substantially equals a sum of integer multiples of a sleep cycle and integer multiplies of the short cycle; wherein the output cycle differs from any integer multiples of the sleep cycle; wherein the sleep cycle characterizes a sleep clock signal that is generated by a low frequency sleep clock; wherein the short cycle is shorter than the sleep cycle; (ii) counting short cycles and sleep cycles; and (iii) generating, during a sleep mode, in response to the counting and to a predefined counting pattern, the first clock signal; wherein the generating includes activating the adjustable ring oscillator only during a portion of a single sleep cycle per each output cycle.