Ring Oscillator Delay Circuit for Precise SRAM Transistor Measurement
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Solution Overview
Problem
Existing methods for measuring the delay characteristics of transistors in semiconductor integrated circuits, such as those in SRAM, are imprecise due to the low proportion of delay contributed by the target transistor, which is limited by the increased load on other transistors when attempting to enhance its delay.
Innovation Solution
A semiconductor integrated circuit device with a ring oscillator having multiple stages of delay circuits, where each circuit includes specific transistor configurations and load capacitance adjustments to increase the proportion of delay contributed by the target transistor, enhancing measurement precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the load connected to the output of the target transistor is increased to increase its delay proportion, then the delay proportion of the target transistor increases, but the loads of other transistors are also increased, limiting the improvement
Solution Approach 1:
The delay circuit is segmented into distinct functional regions: the target transistor region with increased load capacitance for measurement, and other transistor regions with normal loading. This segmentation allows the target transistor's delay to be isolated and measured with higher precision without adversely affecting other transistors.
Solution Approach 2:
The load capacitance is applied locally only to the output of the target transistor rather than uniformly to all transistors. This local quality enhancement increases the delay proportion of the target transistor specifically, improving measurement precision without increasing the loads of other transistors.
2Measurement precision
If transistors in SRAM are incorporated into a delay circuit to measure delay characteristics, then the measurement can be performed, but the proportion of delay caused by the target transistor remains low due to four transistors in one period
Solution Approach 1:
The ring oscillator dynamically operates with an adjustable number of stages. By increasing the number of delay circuit stages in the ring oscillator, the measurement system can accumulate more delay cycles, thereby increasing the proportion of target transistor delay in the total oscillation period and improving measurement precision.
Solution Approach 2:
The load capacitance parameter is specifically increased at the target transistor output to change the delay characteristics. This parameter change increases the delay proportion of the target transistor in the oscillation period, improving measurement precision without requiring changes to other transistor parameters.
Data Source
AI summary
A semiconductor integrated circuit device includes a ring oscillator having a plurality of stages of delay circuits. In each of the delay circuits, when the signal at the input terminal makes a first transition, the signal at the output terminal transitions in response to the operation of a first transistor that corresponds to a transistor in an SRAM cell. When the signal at the input terminal makes a second transition, the first transistor is electrically isolated from the output terminal, and the signal at the output terminal transitions in response to the operation of a second transistor.