Ring Oscillator Delay Measurement with Staged Power Switching

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Solution Overview

Problem

The operating currents between adjacent stages in a CMOS NOT gate ring oscillator affect the performance and reliability of each inverter stage, making it difficult to determine the performance parameters accurately.

Innovation Solution

A delay measurement circuit with a control oscillation module and a target oscillating module, where each stage of the target units is disconnected from the target potential within a first preset time T1 and then connected to it within a second preset time T2, maintaining a logic level for T2, to reduce leakage current and avoid interaction between adjacent stages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a ring oscillator using CMOS NOT gate is used, then the circuit structure is simple and easy to integrate, but the operating currents between adjacent stages affect each other, making it difficult to determine performance parameters accurately

Engineering Contradiction:
Improvecircuit structure simplicityVSAvoidperformance parameter determination accuracy
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The patent divides the ring oscillator into a control oscillation module and a target oscillating module. The control oscillation module generates control signals with specific timing characteristics (cycle time T, with high-level time T1 and low-level time T2) that are used to control the switching of target units in the target oscillating module. This segmentation allows independent optimization of control signal timing to prevent current interaction between adjacent stages, thereby improving measurement precision while maintaining the simplicity of the overall circuit structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The control oscillation module generates control signals in advance with predetermined timing characteristics before they are applied to the target oscillating module. The control signals are designed with specific high-level time T1 and low-level time T2 to ensure that adjacent target units switch at appropriate times, preventing current interaction. This preliminary preparation of control signals with optimized timing resolves the contradiction by enabling accurate performance parameter measurement without complicating the circuit structure.

Inventive Principle:
Principle #10Preliminary action

2Duration of action of stationary object

If adjacent stages are connected continuously, then the circuit operates continuously, but leakage current increases during level transitions

Engineering Contradiction:
Improvecontinuous operationVSAvoidleakage current
Core Design Contradiction:
Duration of action of stationary objectVSLoss of energy

Solution Approach 1:

The control oscillation module generates periodic control signals with cycle time T, where each signal has a high-level period T1 and a low-level period T2. These periodic control signals are applied to the target oscillating module to control the switching of target units. The periodic nature ensures continuous operation while the controlled timing of level transitions minimizes leakage current during switching events.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent dynamically controls the switching of target units using time-varying control signals. The control signals transition between high and low levels at specific times, dynamically controlling when target units connect to or disconnect from power/ground. This dynamic control allows the circuit to operate continuously while minimizing leakage current by ensuring proper timing of transitions, where T1 and T2 are optimized to reduce simultaneous conduction of complementary transistors.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12413216B2Delay measurement circuit and its control method
Publication Date: 2025.09.09 CHANGXIN MEMORY TECH INC
  • US12413216B2 patent drawing
  • US12413216B2 patent drawing
  • US12413216B2 patent drawing

AI summary

A delay measuring circuit includes a control oscillation module with its input terminal connected to its output terminal, which sequentially generates a number of time delay signals with a cycle time T after receiving first enable control signal; a target oscillating module receives a second enabling signal delayed by a first preset threshold than the first enabling signal; after the first preset time T1 is disconnected from the ground terminal/power supply terminal, each stage of the target unit in the target oscillating module connects at the second preset time T2. The level of the target unit turns over at first preset time T1, and target unit maintains logic level for second preset time T2; T1+T2=T/2, and N is an odd integer. So leakage current is reduced and mutual influence of the action current between the adjacent two-level target units are avoided, thus improving ring oscillator performance and reliability.