Ring Oscillator TDC Decoding for PLL Metastability Correction

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Solution Overview

Problem

Digital phase-locked loops (PLLs) with embedded time-to-digital converters (TDCs) face issues with metastability, leading to invalid codes that result in poor jitter performance, slower lock times, and instability, often requiring additional complex circuitry or code discarding, which increases power consumption and affects PLL adjustment.

Innovation Solution

A digital PLL system with an embedded TDC that decodes invalid codes to the closest valid code, utilizing a ring oscillator with an odd number of inverters and a decoder to provide valid codes to the phase frequency detector, reducing metastability issues and improving PLL stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional complex circuitry is added to correct metastability, then PLL stability is improved, but device complexity increases

Engineering Contradiction:
ImprovePLL stabilityVSAvoidcircuitry complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system uses the existing ring oscillator structure with an odd number of inverters to self-correct metastability issues. The inherent property of odd-stage ring oscillators ensures that the TDC code naturally resolves to a valid state without requiring external correction circuitry, making the system self-sufficient in handling metastability.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent changes the structural parameter of the ring oscillator by specifying an odd number of inverters. This parameter change fundamentally alters the behavior of the TDC, ensuring that metastable states cannot persist and the system automatically produces valid codes, thereby improving reliability without adding complexity.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If invalid codes are discarded to improve PLL performance, then measurement precision is improved, but loss of information increases

Engineering Contradiction:
Improvephase measurement accuracyVSAvoidphase information loss
Core Design Contradiction:
Measurement precisionVSLoss of information

Solution Approach 1:

The patent converts the potentially harmful metastable states into a beneficial feature by using the odd-numbered ring oscillator structure. Instead of discarding invalid codes, the system's inherent structure ensures that the TDC naturally produces valid codes even during metastable transitions, transforming what would be information loss into maintained measurement precision.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If additional circuitry is added to handle metastability, then reliability is improved, but power consumption increases

Engineering Contradiction:
ImprovePLL stabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The odd-stage ring oscillator structure provides self-service by inherently preventing metastable states from causing invalid TDC codes. No additional active correction circuitry is needed, thus avoiding the power consumption that would result from continuously operating correction mechanisms.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

By changing the structural parameter to an odd number of inverters, the system achieves reliability improvement passively. This parameter change eliminates the need for power-hungry active correction circuits, maintaining low power consumption while ensuring stable operation.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11863193B2Metastability correction for ring oscillator with embedded time to digital converter
Publication Date: 2024.01.02 TEXAS INSTRUMENTS INC
  • US11863193B2 patent drawing
  • US11863193B2 patent drawing
  • US11863193B2 patent drawing

AI summary

A system includes a ring oscillator including an odd number of inverters arranged in a ring. The system also includes a time to digital converter including an odd number of flops, where each of the flops is coupled to an output of a different inverter. The system includes a level shifter coupled to the inverters and to the flops. The system also includes a Gray counter coupled to at least one of the flops. The system includes a decoder coupled to the time to digital converter. The system also includes a phase frequency detector coupled to the decoder.