Ring Oscillator TDC Architecture for Low-Power Linear Conversion
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Solution Overview
Problem
Conventional time-to-digital converters (TDCs) face challenges in achieving optimal design parameters such as low area occupation and low power consumption while maintaining linearity, with delay chain TDCs offering poor linearity and large area, and cyclic TDCs requiring power-hungry circuitry.
Innovation Solution
The proposed TDC design incorporates a ring oscillator and a residue generation circuit with an equal number of stages, a counter that counts signal transitions, and a combiner that generates digital values by combining counter outputs with residue generation outputs, allowing for low area and power consumption while maintaining linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If delay chain TDC is used, then device complexity is reduced, but measurement precision deteriorates due to poor linearity and large area occupation
Solution Approach 1:
The TDC is divided into multiple independent delay stages, each contributing to the overall time measurement. The segmentation of the delay chain into discrete stages allows for better linearity control while maintaining manageable device complexity.
Solution Approach 2:
The patent transitions from a simple linear delay chain to a multi-dimensional structure by incorporating parallel delay paths and hierarchical organization of delay elements, improving linearity without proportionally increasing area occupation.
2Device complexity
If delay chain TDC is used, then device complexity is reduced, but area occupation increases
Solution Approach 1:
Delay elements are nested within a hierarchical structure where smaller delay units are organized into larger functional blocks. This nesting allows compact area occupation while maintaining the required number of delay stages for accurate measurement.
Solution Approach 2:
The delay chain is organized in a multi-dimensional layout with parallel paths and hierarchical grouping, reducing the linear area occupation while preserving the total number of delay stages needed for the measurement range.
3Area of stationary object
If cyclic TDC is used, then area occupation is reduced, but use of energy increases due to power-hungry circuitry
Solution Approach 1:
The TDC operates in periodic cycles where the delay chain is activated only when needed for measurement, allowing the use of lower-power delay elements that can be switched on and off rather than continuously operating high-power circuitry.
Solution Approach 2:
The patent employs simple, low-cost delay elements that can be rapidly switched rather than expensive, continuously-operating high-power circuitry. Each measurement cycle uses fresh delay stage activations, allowing the use of energy-efficient but simpler components.
4Area of stationary object
If cyclic TDC is used, then area occupation is reduced, but device complexity increases due to power-hungry circuitry requirements
Solution Approach 1:
The cyclic TDC architecture is segmented into modular functional blocks that can be independently controlled and optimized. This segmentation reduces the need for complex interconnections and control logic while maintaining compact area occupation.
Data Source
AI summary
TDCs for converting time periods to digital values are disclosed. An example TDC includes a ring oscillator and a residue generation circuit. Each stage of the residue generation circuit is configured to operate on outputs from two different stages of the ring oscillator. The TDC further includes a counter for counting the number of times that an output of one of the stages of the ring oscillator switches between being at a first signal level and being at a second signal level during a time period that is being converted to a digital value. The TDC also includes a combiner for generating the digital value by combining a value indicative of the number of times counted by the counter and an output of the residue generation circuit. Such a TDC may have relatively low area and low power consumption compared to the conventional TDC designs, while yielding sufficiently linear behavior.