Ring-Oscillator TDC With Periodic Sampling and Error Correction

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Solution Overview

Problem

Conventional time-to-digital converters (TDCs) face challenges in achieving high resolution and large dynamic range while maintaining low power consumption and small IC area, with issues such as trade-offs between resolution and dynamic range, linearity problems due to inverter mismatches, and power wastage in ring oscillator-based designs.

Innovation Solution

A recirculating TDC design that includes a ring oscillator module with a digital error correction module, operating in two modes to switch the ring oscillator on and off based on a preset signal, and using a digital control module with a pseudo-random code generator to address inverter mismatches and miscounting errors, thereby improving linearity and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the number of inverter stages is increased to extend dynamic range, then dynamic range is improved, but power consumption increases and IC area increases

Engineering Contradiction:
Improvedynamic rangeVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The ring oscillator is operated in periodic on-off cycles, remaining off during idle periods and only activating during measurement intervals. This periodic operation allows the TDC to maintain large dynamic range capability while dramatically reducing average power consumption compared to continuously operating delay-line TDCs.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The invention dynamically switches the ring oscillator between on and off states based on operational needs. The oscillator can be enabled for measurement periods and disabled during idle periods, creating a dynamic power management system that adapts to workload requirements and reduces overall power consumption.

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If the number of inverter stages is increased to extend dynamic range, then dynamic range is improved, but IC area increases

Engineering Contradiction:
Improvedynamic rangeVSAvoidIC area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

By using periodic on-off operation of the ring oscillator, the design achieves large dynamic range with fewer physical inverter stages. The time-domain multiplexing approach allows a compact oscillator to provide measurements across a wide range, reducing the IC area required compared to static delay-line designs that need many parallel stages.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The invention embeds multiple measurement capabilities within a single ring oscillator structure by utilizing different operating modes and recirculating configurations. This nesting allows one compact oscillator to perform the function of what would traditionally require multiple separate delay elements, reducing overall IC area.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Measurement precision

If inverter stages are increased to extend dynamic range, then dynamic range is improved, but linearity deteriorates due to mismatch

Engineering Contradiction:
Improvedynamic rangeVSAvoidlinearity
Core Design Contradiction:
Measurement precisionVSManufacturing precision

Solution Approach 1:

The digital error correction module implements feedback mechanisms that detect and correct non-linearity errors in the TDC output. By monitoring the relationship between input time intervals and digital codes, the system identifies mismatches and applies correction algorithms to restore linearity, enabling accurate measurements across the full dynamic range.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The invention changes the operating parameters of the ring oscillator, including frequency and duty cycle, to optimize performance across different measurement ranges. By dynamically adjusting these parameters, the system maintains linearity while achieving large dynamic range, avoiding the need for excessive inverter stages that would introduce mismatch errors.

Inventive Principle:
Principle #35Parameter changes

4Reliability

If ring oscillator operates continuously to provide measurements, then measurement capability is maintained, but power consumption increases

Engineering Contradiction:
Improvemeasurement capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The ring oscillator operates periodically rather than continuously, being activated only during measurement intervals and remaining in a low-power off state during idle periods. This periodic operation maintains measurement capability when needed while dramatically reducing average power consumption compared to continuous operation.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The TDC system includes idle detection circuitry that automatically detects when no measurement is required and disables the ring oscillator accordingly. This self-service mechanism ensures the oscillator remains active only when measurements are needed, eliminating wasteful continuous operation and reducing power consumption.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11042126B2Time-to-digital converter
Publication Date: 2021.06.22 HUAWEI INT PTE LTD
  • US11042126B2 patent drawing
  • US11042126B2 patent drawing
  • US11042126B2 patent drawing

AI summary

A time-to-digital converter (TDC) is disclosed, which comprises a ring oscillator module and a digital error correction module. The ring oscillator module is configured to receive a sampling signal, an addressing signal, and a preset signal, and includes: a ring oscillator arranged with a plurality of inverters; a phase sampler configured to sample phase signals generated by the inverters for generating a first output signal; a counter clock generator configured to generate first and second clock signals; first and second counters configured to respectively generate first and second counter output signals; and a data sampler configured to sample the first and second counter output signals to respectively generate second and third output signals. The digital error correction module is arranged to process the first, second and third output signals for generating a digital signal.