Ring Oscillator TDC Architecture for Low-Power Linear Timing
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Solution Overview
Problem
Conventional time-to-digital converters (TDCs) face challenges in achieving low area and low power consumption while maintaining linearity, with delay chain TDCs offering poor linearity and large surface area, and cyclic TDCs requiring power-hungry circuitry.
Innovation Solution
The proposed TDC design includes a ring oscillator and a residue generation circuit with an equal number of stages, a counter that operates on the output of one stage of the ring oscillator, and a combiner that generates a digital value by combining the counter's output with the residue generation circuit's output, allowing for low area and power consumption while maintaining linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If delay chain TDC design is used, then the TDC can be implemented with simple circuitry, but the linearity is poor and surface area is large
Solution Approach 1:
The TDC is segmented into multiple independent delay stages, each contributing to the overall time measurement. By dividing the measurement function across multiple stages with individual delay elements, the design achieves both simplicity in each stage and improved linearity in the aggregate measurement, resolving the contradiction between circuit simplicity and measurement precision.
2Ease of manufacture
If delay chain TDC design is used, then the circuit implementation is straightforward, but the surface area occupied is large
Solution Approach 1:
Multiple delay stages are merged into a unified ring oscillator structure where the output of one stage feeds into the next in a closed loop. This combining approach reduces the total surface area compared to separate delay chains while maintaining the segmented measurement functionality, and simplifies implementation by using a regular repeating structure.
3Manufacturing precision
If cyclic TDC design is used, then the TDC achieves better linearity, but power consumption increases
Solution Approach 1:
The TDC uses periodic clock signals to drive the ring oscillator and control the measurement process. By employing periodic enable signals that activate the oscillator only during measurement intervals, the design achieves consistent linear timing measurements while minimizing power consumption during non-measurement periods, resolving the contradiction between linearity and power usage.
Data Source
AI summary
TDCs for converting time periods to digital values are disclosed. An example TDC includes a ring oscillator and a residue generation circuit. Each stage of the residue generation circuit is configured to operate on outputs from two different stages of the ring oscillator. The TDC further includes a counter for counting the number of times that an output of one of the stages of the ring oscillator switches between being at a first signal level and being at a second signal level during a time period that is being converted to a digital value. The TDC also includes a combiner for generating the digital value by combining a value indicative of the number of times counted by the counter and an output of the residue generation circuit. Such a TDC may have relatively low area and low power consumption compared to the conventional TDC designs, while yielding sufficiently linear behavior.