Ring Oscillator Shift Register for Precise Low-Power Time Sequences
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Solution Overview
Problem
Existing time sequence generation circuits are bulky, consume high power, and are complex to implement, especially when generating adjustable time sequences with high precision, due to the use of numerous flip-flops and high-frequency oscillators.
Innovation Solution
A circuit design incorporating a ring oscillator with a first shift register looped back to form a second oscillator, synchronized to a slower clock signal, and a second shift register synchronized to a fast clock signal, allowing for adjustable time sequences with reduced flip-flop count and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a microprocessor operating at several GHz with phase-locked loop systems is used to generate time sequences with picosecond timescale precision, then the time sequence generation precision is improved, but the power consumption and manufacturing cost increase significantly
Solution Approach 1:
The patent replaces expensive, high-power microprocessor-based PLL systems with a simple ring oscillator composed of basic logic gates (inverters, NAND gates, or NOR gates). This ring oscillator generates clock signals directly without requiring complex phase-locked loop circuitry, thereby dramatically reducing power consumption and manufacturing cost while achieving acceptable timing precision for the application
Solution Approach 2:
The patent substitutes the mechanical/electronic complex system (microprocessor with PLL) with a simpler electronic oscillation system based on logic gate feedback. The ring oscillator uses the inherent propagation delays of logic gates to generate periodic clock signals, eliminating the need for complex control circuits and high-frequency microprocessors
2Use of energy by moving object
If a ring oscillator with multiple logic gates is used to generate time sequences, then the power consumption is reduced, but the device complexity increases due to the need for multiple flip-flops and multiplexers
Solution Approach 1:
The patent segments the time sequence generation function into two independent parts: (1) a ring oscillator that generates multiple clock signals with different phase offsets, and (2) a selection mechanism that chooses the appropriate clock signal based on the desired time sequence. This segmentation allows each part to be optimized independently, reducing overall complexity
Solution Approach 2:
The ring oscillator is designed to simultaneously generate multiple clock signals (CK1, CK2, CK3, CKN-1, CKN) with different phase offsets, making it a multi-functional component. A single ring oscillator structure provides all the timing signals needed for different time sequence requirements, eliminating the need for separate oscillators for each time slot
3Adaptability or versatility
If numerous flip-flops are used in the shift register to achieve adjustable time sequences, then the time sequence adjustability is improved, but the circuit area and power consumption increase
Solution Approach 1:
The patent makes the system dynamic by allowing the selection of different clock signals from the ring oscillator based on the desired time sequence. Instead of having fixed, dedicated flip-flops for each possible time offset, the system dynamically selects the appropriate clock phase to achieve the required timing, enabling adjustability without proportionally increasing circuit area
Solution Approach 2:
The patent discards the conventional approach of using numerous flip-flops to store and shift data for time sequencing. Instead, it recovers timing information by selecting from pre-generated clock phases, effectively discarding the need for large numbers of storage elements while maintaining time sequence adjustability
Data Source
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AI summary
This description relates to a device (200) comprising a ring oscillator (RO) with a plurality of gates (II, INf), each providing a fast clock signal (CKfl, CkfNf). A first shift register (OSC) comprises a series of first flip-flops (FFsl, FFsNS), each synchronized to the same first clock signal (CKl) corresponding to one of the fast clock signals (CKfl, CkfNf). The first shift register (OSC) is fed back into itself and implements a second oscillator where each first flip-flop (FFsl, FFsNs) provides a slow clock signal (CKs1, CKsNs). A second shift register (SR) comprises a series of second flip-flops (FF1, FFNdl), each synchronized to the same second clock signal (CKs) corresponding to one of the slow clock signals (CKs1, CKsNs).