Ring-Oscillator Timing Block for Glitch-Free Capacitor Tuning
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Solution Overview
Problem
Conventional ring-oscillators experience glitches during frequency tuning due to asynchronous timing of capacitor connection, leading to voltage changes and performance issues in applications like phase-lock-loops and digital circuitry.
Innovation Solution
A ring-oscillator design with multiple delay stages and capacitor banks, where timing blocks synchronize the connection or disconnection of capacitors to the ring loop based on the output signal conditions, ensuring no significant voltage change beyond a threshold, thus eliminating glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If capacitors are connected or disconnected asynchronously during frequency tuning, then the frequency can be adjusted, but voltage changes cause glitches at the output
Solution Approach 1:
The timing block monitors the output signal of the first delay stage and only allows capacitor switching when the signal meets a specific condition (e.g., is at a stable logic level). This preliminary check ensures that capacitor connection/disconnection occurs at the optimal moment, preventing voltage transitions that would cause glitches while still enabling frequency tuning.
2Reliability
If capacitor switching is synchronized to output signal conditions, then glitches are eliminated, but the timing block adds circuit complexity
Solution Approach 1:
The timing block acts as an intermediary between the frequency control signal and the capacitor bank. It receives the frequency tuning command and the output signal condition, then generates the appropriate switching control signal only when conditions are met. This intermediary approach eliminates glitches while adding minimal complexity compared to the alternative of completely asynchronous switching.
3Measurement precision
If frequent capacitor updates are performed for precise frequency control, then frequency accuracy improves, but power consumption increases due to asynchronous switching
Solution Approach 1:
The timing block enables capacitor updates to occur periodically at specific phases of the oscillation cycle rather than continuously or asynchronously. By gating the capacitor switching to occur only when the output signal is at the appropriate level, the system achieves precise frequency control while minimizing the number of switching events and associated power consumption.
Data Source
AI summary
The present disclosure relates to a ring-oscillator with glitch-free frequency-tuning. The disclosed ring-oscillator at least includes multiple delay stages coupled in series within a ring loop and having a first delay stage, a capacitor bank coupled between an output of the first delay stage and ground, and a timing block configured to receive an output signal of the first delay stage and at least one controlling signal. The at least one controlling signal determines at least one capacitor in the capacitor bank connecting or disconnecting to the ring loop. The timing block is configured to pass or not pass the at least one controlling signal to the capacitor bank based on whether the output signal of the first delay stage meets a certain condition. Therefore, the connection or disconnection of the at least one capacitor does not cause a significant voltage change at the output of the first delay stage.