Ring Oscillator Shift Register Timing for Low-Power Sequence Generation
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Solution Overview
Problem
Existing time sequence generation circuits face challenges in generating adjustable time sequences with moderate costs, while minimizing power consumption and circuit surface area, and are complex to implement due to the need for high-frequency oscillators and numerous flip-flops.
Innovation Solution
A circuit design incorporating a ring oscillator with a first shift register looped back to form a second oscillator, synchronized to a fast clock signal, and a second shift register synchronized to a slow clock signal, allowing for adjustable time sequences with reduced flip-flop count and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a microprocessor at several GHz with phase-locked loop systems is used to generate time sequences, then time sequence precision is improved, but manufacturing cost and power consumption increase
Solution Approach 1:
The patent replaces expensive high-frequency phase-locked loop systems with a more economical approach using a ring oscillator at lower frequency (e.g., 100 MHz) combined with shift registers. This substitutes costly, power-intensive components with simpler, cheaper components that achieve the same time sequence generation function through software-controlled delay stages rather than hardware frequency multiplication
Solution Approach 2:
The patent changes the operating frequency parameter from several GHz to a lower frequency (e.g., 100 MHz) and compensates by increasing the number of delay stages in the shift register. This parameter transformation allows achieving the same time sequence precision through a different operational regime that consumes less power
2Measurement precision
If a microprocessor at several GHz with phase-locked loop systems is used to generate time sequences, then time sequence precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive high-frequency phase-locked loop systems with a more economical approach using a ring oscillator at lower frequency (e.g., 100 MHz) combined with shift registers. This substitutes costly, power-intensive components with simpler, cheaper components that achieve the same time sequence generation function through software-controlled delay stages rather than hardware frequency multiplication
Solution Approach 2:
The patent substitutes the mechanical/electrical high-frequency phase-locked loop system with a software-controlled delay line implementation. The time sequence generation is achieved through programmed delay stages in shift registers rather than through complex analog frequency synthesis hardware, reducing manufacturing complexity and cost
3Adaptability or versatility
If numerous flip-flops are used to generate adjustable time sequences, then time sequence adjustability is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic control of the delay line through software programming of the shift register stages, allowing the delay length to be adjusted dynamically without changing the physical circuit structure. The same hardware configuration can be reconfigured via control signals to provide different time sequence lengths, replacing static multiple fixed delay lines with a single programmable delay line
Solution Approach 2:
The patent creates a universal time sequence generator where a single ring oscillator and shift register configuration can generate multiple different time sequences through software control. The same hardware components serve multiple functions by being programmably configured for different delay lengths and time sequence patterns, eliminating the need for separate dedicated circuits for each time sequence
4Measurement precision
If high-frequency oscillators are used to generate time sequences, then time sequence precision is improved, but power consumption increases
Solution Approach 1:
The patent replaces expensive high-frequency phase-locked loop systems with a more economical approach using a ring oscillator at lower frequency (e.g., 100 MHz) combined with shift registers. This substitutes costly, power-intensive components with simpler, cheaper components that achieve the same time sequence generation function through software-controlled delay stages rather than hardware frequency multiplication
Solution Approach 2:
The patent changes the operating frequency parameter from several GHz to a lower frequency (e.g., 100 MHz) and compensates by increasing the number of delay stages in the shift register. This parameter transformation allows achieving the same time sequence precision through a different operational regime that consumes less power
Data Source
AI summary
The present description concerns a device comprising a ring oscillator comprising a plurality of gates, each delivering a fast clock signal. A first shift register comprises a succession of first flip-flops, each synchronized to a same first clock signal corresponding to one of the fast clock signals. The first shift register is looped back on itself and implements a second oscillator where each first flip-flop delivers a slow clock signal. A second shift register comprises a succession of second flip-flops, each synchronized to the same second clock signal corresponding to one of the slow clock signals.