Ring Oscillator TRNG Circuit With Metastability Filtering
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Solution Overview
Problem
Existing coherent sampling ring oscillator-based true random number generation circuits fail to account for metastabilities in flip-flops, leading to inaccurate stochastic models and operational deviations due to metastability noise.
Innovation Solution
Incorporating a metastability management circuit to remove output values resulting from metastabilities in flip-flops and reset the counter at specific edges, using a metastability management circuit to generate a metastability-free signal by filtering out values below a threshold determined by setup and hold times, and implementing a majority vote between delayed samples.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a flip-flop samples a signal edge too close to the clock signal edge, then metastability occurs which can be used as an entropy source, but metastability noise degrades the accuracy of stochastic modeling and entropy source characterization
Solution Approach 1:
The patent extracts and removes metastability-induced output values from the counter using a dedicated metastability management circuit. The circuit identifies and eliminates values below a threshold that result from metastability events, separating the harmful metastability noise from the useful random number generation output.
Solution Approach 2:
The patent introduces a metastability management circuit as an intermediary between the flip-flop and the counter output. This circuit acts as a mediator that filters out metastability-induced errors while preserving the legitimate random values, using threshold comparison based on setup and hold time parameters.
2Measurement precision
If the counter is reset at every flip-flop output edge, then the counter tracks phase differences accurately, but metastability events cause incorrect resets and degrade measurement precision
Solution Approach 1:
The patent performs preliminary detection and removal of metastability-induced values before they can corrupt the counter measurement process. The metastability management circuit proactively identifies and eliminates invalid output values based on threshold comparison, preventing them from causing incorrect counter resets.
Solution Approach 2:
The patent uses feedback from the flip-flop output to control the counter reset operation. The metastability management circuit monitors the flip-flop output and conditionally generates reset signals to the counter only when valid transitions occur, using feedback from threshold comparisons of the output values.
3Device complexity
If no metastability filtering is applied, then the circuit complexity remains low, but the stochastic models become inaccurate and entropy source characterization is compromised
Solution Approach 1:
The patent changes the operational parameters of the existing circuit by introducing threshold-based filtering. Instead of fundamentally redesigning the architecture, it modifies the behavior by comparing output values against calculated thresholds derived from setup and hold times, thereby improving accuracy while maintaining structural simplicity.
Data Source
AI summary
The present description concerns a circuit (3). First and second identical ring oscillators (R1, R0) deliver first and second periodic signals (S1, S0). A flip-flop (102) samples the first signal (S1) at the beginning of each period of the second signal (S0). A counter (COUNTER) is clocked by the second signal (S0). A metastability management circuit (GM) removes output values (N) of the counter resulting from metastabilities of the first flip-flop (102), and resets the counter (COUNTER) at each rising edge and/or at each falling edge of an output (Beat) of the first flip-flop (102).