Ring Oscillator TRNG Sampling Reset for Faster Entropy Capture
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Solution Overview
Problem
Existing ring oscillator-based True Random Number Generators (TRNGs) face limitations in achieving faster sampling speeds due to the use of standard cells, leading to stuck sampling and inefficiencies in entropy collection.
Innovation Solution
A method for designing a TRNG using a predefined standard cell library, incorporating a sampling circuit with a reset and selecting appropriate storage elements from the library to allow for higher operating frequencies, including the use of flops or latches with built-in reset functionality or additional gates for reset configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard cells are used to design TRNG sampling circuitry, then ease of manufacture is improved, but sampling speed is limited and cannot achieve faster operating frequencies
Solution Approach 1:
The patent changes the parameters of the storage element by adding a reset mechanism and carefully selecting operating conditions (sampling frequency relative to oscillator frequency) to enable faster sampling speeds while maintaining compatibility with standard cell manufacturing processes. This allows the circuit to operate at higher frequencies without requiring non-standard manufacturing approaches.
2Productivity
If sampling frequency is increased to achieve faster entropy collection, then productivity is improved, but the sampling circuit becomes unable to accurately capture entropy due to insufficient time for oscillator phase drift
Solution Approach 1:
The patent introduces dynamic control through the reset mechanism that adapts the sampling circuit's operation to the oscillator's phase drift characteristics. The reset functionality allows the circuit to dynamically adjust its sampling window to capture entropy effectively even at higher frequencies where phase drift occurs more rapidly.
Solution Approach 2:
The patent carefully selects and adjusts critical parameters including the sampling frequency (set to a fraction of the oscillator frequency), oscillator length, and reset timing to ensure that sufficient phase drift occurs during each sampling interval, maintaining sampling accuracy while enabling faster overall operation.
3Device complexity
If standard flops are used in sampling circuitry, then device complexity is reduced, but the circuit cannot support higher operating frequencies required by modern cryptographic applications
Solution Approach 1:
The patent segments the sampling operation into controlled phases using the reset mechanism, separating the entropy capture function from the standard flop operation. This segmentation allows the use of simple standard flops while achieving higher effective operating frequencies through multiple controlled sampling phases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables TRNGs to operate at higher frequencies while maintaining security and efficiency, allowing for faster entropy collection and improved performance in cryptographic applications.
Implementation Method 1
Free-running ring oscillators are not locked to other clocks and can accumulate jitter due to many unpredictable effects, including thermal noise
Implementation Method 2
By sampling the ring oscillator at a sufficiently low frequency such that the phase of the oscillator can drift more than a full oscillation period in the average, it is possible to generate entropy
Data Source
AI summary
A true random number generator (TRNG) as described herein can include a ring oscillator; and a sampling circuit coupled to an intermediate node of the ring oscillator, wherein the sampling circuit includes a reset, wherein the ring oscillator and the sampling circuit are formed of components from a standard cell library. The sampling circuit includes a storage cell selected for having a shortest oscillation period of a data input of the storage cell that results in a non-constant output. The reset of the sampling circuit can include a logic gate or be built-in reset functionality of the storage cell.