Ring Oscillator Test Architecture for Stacked TSV Characterization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current interconnect testing technologies for stacked integrated circuits face challenges in efficiently testing hundreds of through-silicon vias (TSVs) due to high test time, silicon area, and routing complexities, which can lead to defective TSVs and reduced chip yield, especially due to thermal stress and imperfect etching processes.
Innovation Solution
A ring-oscillator-based test architecture that utilizes boundary scan cells configured as asynchronous counters to dynamically form counters for parallel testing of TSVs, reducing silicon area and routing overhead, and enabling efficient pre-bond and post-bond testing by configuring ring oscillators with control circuitry and multiplexers to measure oscillation periods accurately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional interconnect testing methods are used for hundreds of TSVs, then testing coverage can be achieved, but test time becomes excessively long and silicon area overhead increases
Solution Approach 1:
The patent combines multiple testing functions into a unified ring oscillator-based test architecture. Boundary scan cells are merged with ring oscillator circuits, allowing simultaneous testing of multiple TSVs through parallel oscillation frequency measurements. This consolidation reduces test time while maintaining comprehensive TSV coverage through the efficient use of shared test resources.
Solution Approach 2:
The test architecture dynamically configures ring oscillators to test different TSV combinations. The system can reconfigure which TSVs are activated and measured in each test cycle, enabling adaptive testing strategies that optimize test time based on detected defects. This dynamic approach allows the system to focus on critical TSVs first and reduce overall test duration.
2Measurement precision
If dedicated test circuits are added for each TSV, then testing precision improves, but silicon area overhead becomes excessive
Solution Approach 1:
The ring oscillator circuits serve multiple functions: they act as both the test stimulus source and the measurement device. The same boundary scan cells used for functional testing are repurposed to measure oscillation frequencies. This multi-functionality eliminates the need for dedicated test circuits for each TSV, reducing silicon area overhead while maintaining precise TSV characterization through frequency measurements.
Solution Approach 2:
The test architecture uses the device's own boundary scan cells and logic structures to perform TSV testing. Rather than requiring external dedicated test equipment or additional circuitry, the system leverages existing resources to measure TSV properties. The ring oscillators self-generate test signals and the boundary scan cells self-measure the resulting frequencies, minimizing area overhead.
3Measurement precision
If complex routing is implemented to access all TSVs, then testing completeness improves, but device complexity and routing overhead increase
Solution Approach 1:
The TSV testing is segmented into groups that can be tested in parallel through the ring oscillator architecture. Instead of requiring complex routing to access each TSV individually, the system divides TSVs into testable groups and uses systematic activation patterns. This segmentation simplifies routing requirements while maintaining testing completeness through structured test sequences.
Solution Approach 2:
The test system uses periodic activation of ring oscillators to systematically test different TSV groups. By activating oscillators in regular patterns and measuring their frequencies over time, the system achieves complete TSV coverage without requiring complex simultaneous routing. The periodic nature of the tests allows simple routing to be reused across multiple test cycles.
Data Source
AI summary
The disclosed ring-oscillator-based test architecture comprises a plurality of boundary scan cells coupled to a plurality of interconnects and control circuitry. Each of the plurality of boundary scan cells can be configured to operate as, based on control signals, a conventional boundary scan cell or any bit of an asynchronous counter. The control signals are supplied by the control circuitry.